Patents by Inventor Jong-Pyo Kim

Jong-Pyo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8303704
    Abstract: A siloxane based coating composition having excellent dyeability, abrasion resistance, glossiness and transparency, a preparation method thereof, and an optical lens coated by the coating composition are suggested. The siloxane based coating composition includes organo silane compound, inorganic oxide (H-index filler), solvent and a dyeing improving material. The dyeing improving material adopts nitric acid, hydrochloric acid, phosphoric acid, sodium nitrate, potassium nitrate, silver nitrate, or the like. The siloxane based coating composition shows excellent dyeability owing to the dyeing improving material, excellent abrasion resistance owing to the organo silane compound, and excellent glossiness and transparency, so it may be applied as a coating film on a surface of a plastic lens such as optical lens, industrial safety lens and leisure-purpose goggle that require high transparency.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: November 6, 2012
    Assignee: LG Chem, Ltd.
    Inventors: Sang-Hyuk Im, Do-Hyun Jin, Jong-Pyo Kim, Young-Jun Hong, Seung-Heon Lee
  • Patent number: 8115262
    Abstract: A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric layer which is formed on top of the lower dielectric layer and which is made of amorphous metal oxide (M?Oy) or amorphous metal oxynitride (M?OyNz).
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: February 14, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Pyo Kim, Jong-Ho Lee, Hyung-Suk Jung, Jung-Hyoung Lee
  • Patent number: 7928482
    Abstract: A gate structure includes a gate insulation layer pattern, a gate electrode, a first spacer and a protecting layer pattern. The gate insulation layer pattern is on a substrate. The gate electrode is on the gate insulation layer pattern, the gate electrode including a lower portion having a first width, a central portion having a second width smaller than the first width and an upper portion having a third width. The first spacer is on a lower sidewall of the gate electrode. The protecting layer pattern is on a central sidewall of the gate electrode.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Chul Sun, Jong-Pyo Kim
  • Publication number: 20100064939
    Abstract: A siloxane based coating composition having excellent dyeability, abrasion resistance, glossiness and transparency, a preparation method thereof, and an optical lens coated by the coating composition are suggested. The siloxane based coating composition includes organo silane compound, inorganic oxide (H-index filler), solvent and a dyeing improving material. The dyeing improving material adopts nitric acid, hydrochloric acid, phosphoric acid, sodium nitrate, potassium nitrate, silver nitrate, or the like. The siloxane based coating composition shows excellent dyeability owing to the dyeing improving material, excellent abrasion resistance owing to the organo silane compound, and excellent glossiness and transparency, so it may be applied as a coating film on a surface of a plastic lens such as optical lens, industrial safety lens and leisure-purpose goggle that require high transparency.
    Type: Application
    Filed: November 15, 2007
    Publication date: March 18, 2010
    Applicant: LG CHEM, LTD.
    Inventors: Sang-Hyuk Im, Do-Hyun Jin, Jong-Pyo Kim, Young-Jun Hong, Seung-Heon Lee
  • Patent number: 7651729
    Abstract: There are provided methods of fabricating a metal silicate layer on a semiconductor substrate using an atomic layer deposition technique. The methods include performing a metal silicate layer formation cycle at least one time in order to form a metal silicate layer having a desired thickness. The metal silicate layer formation cycle includes an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon oxide layer formation cycle Q times. K and Q are integers ranging from 1 to 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, exhausting the metal source gas remaining in a reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: January 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Seok Kim, Jong-Pyo Kim, Ha-Jin Lim, Jae-Eun Park, Hyung-Suk Jung, Jong-Ho Lee, Jong-Ho Yang
  • Publication number: 20090267129
    Abstract: A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric layer which is formed on top of the lower dielectric layer and which is made of amorphous metal oxide (M'Oy) or amorphous metal oxynitride (M'OyNz).
    Type: Application
    Filed: July 6, 2009
    Publication date: October 29, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Pyo KIM, Jong-Ho LEE, Hyung-Suk JUNG, Jung-Hyoung LEE
  • Publication number: 20090250774
    Abstract: A gate structure includes a gate insulation layer pattern, a gate electrode, a first spacer and a protecting layer pattern. The gate insulation layer pattern is on a substrate. The gate electrode is on the gate insulation layer pattern, the gate electrode including a lower portion having a first width, a central portion having a second width smaller than the first width and an upper portion having a third width. The first spacer is on a lower sidewall of the gate electrode. The protecting layer pattern is on a central sidewall of the gate electrode.
    Type: Application
    Filed: April 2, 2009
    Publication date: October 8, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sun Min-Chul, Jong-Pyo Kim
  • Patent number: 7588989
    Abstract: A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric layer which is formed on top of the lower dielectric layer and which is made of amorphous metal oxide (M?Oy) or amorphous metal oxynitride (M?OyNz).
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: September 15, 2009
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Jong-Pyo Kim, Jong-Ho Lee, Hyung-Suk Jung, Jung-Hyoung Lee
  • Publication number: 20070128454
    Abstract: The present invention relates to a silicone-based coating composition with middle and high refractive index, a method of preparing the same, and an optical lens prepared therefrom, and more specifically to a silicone-based coating composition including organosilanes, inorganic oxides having a refractive index of from 1.7 to 3.0, an aluminum acetyl acetone, a C1-C5 alkyl cellosolve, and a solvent, a method of preparing the same, and an optical lens prepared therefrom. The siloxane-based coating composition is transparent, not sticky, and stable for long time storage. Therefore, the coating composition can be applied to a coating layer on a surface of a plastic lens such as an optical lens, an industrial safety lens, or goggles for leisure.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 7, 2007
    Inventors: Sang-Hyuk Im, Do-Hyun Jin, Jong-Pyo Kim, Seung-Heon Lee, Young-Jun Hong
  • Publication number: 20070068421
    Abstract: The present invention relates to a silicone-based coating composition improved adhesion and dyeability, and more specifically, to a silicone-based coating composition prepared by adding a compound(s) having at least one functional group selected from the group consisting of amino, carboxylic acid, mercapto, methylol, anhydride, and isocyanate into an organic-inorganic sol prepared by a sol-gel reaction of organosilanes at high temperature, a method of preparing the same, and an optical lens prepared therefrom. The dyeability of the coating composition is improved by conducting sol-gel reaction at high temperature, and the adhesion to the substrate is improved by adding the compound capable of hydrogen bond and condensation reaction. Therefore, the coating layer of the present invention is proper to be applied to a coating layer for a plastic lens such as glasses, an industrial glass, or goggles for leisure because of good dyeability and adhesion to substrate.
    Type: Application
    Filed: December 1, 2006
    Publication date: March 29, 2007
    Inventors: Sang-Hyuk Im, Do-Hyun Jin, Jong-Pyo Kim, Seung-Heon Lee, Young-Jun Hong
  • Publication number: 20070059447
    Abstract: Methods of fabricating a lanthanum oxide layer, and methods of fabricating a MOSFET and/or a capacitor especially adapted for semiconductor applications using such a lanthanum oxide layer are disclosed. The methods include a preliminary step of disposing a semiconductor substrate into a chamber. Tris(bis(trimethylsilyl)amino)Lanthanum as a lanthanum precursor is then injected into the chamber such that the lanthanum precursor is chemisorbed on the semiconductor substrate. Then, after carrying out a first purge of the chamber, at least one oxidizer is injected into the chamber such that the oxidizer is chemisorbed with the lanthanum precursor on the semiconductor substrate. Then, the chamber is purged a second time.
    Type: Application
    Filed: November 14, 2006
    Publication date: March 15, 2007
    Inventors: Jong-Pyo Kim, Jung-Hyun Lee, Bum-Seok Seo, Jung-Hyoung Lee
  • Patent number: 7153786
    Abstract: Methods of fabricating a lanthanum oxide layer, and methods of fabricating a MOSFET and/or a capacitor especially adapted for semiconductor applications using such a lanthanum oxide layer are disclosed. The methods include a preliminary step of disposing a semiconductor substrate into a chamber. Tris(bis(trimethylsilyl)amino)Lanthanum as a lanthanum precursor is then injected into the chamber such that the lanthanum precursor is chemisorbed on the semiconductor substrate. Then, after carrying out a first purge of the chamber, at least one oxidizer is injected into the chamber such that the oxidizer is chemisorbed with the lanthanum precursor on the semiconductor substrate. Then, the chamber is purged a second time.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: December 26, 2006
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Jong-Pyo Kim, Jung-Hyun Lee, Bum-Seok Seo, Jung-Hyoung Lee
  • Publication number: 20060257563
    Abstract: There are provided methods of fabricating a silicon-doped metal oxide layer on a semiconductor substrate using an atomic layer deposition technique. The methods include an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon-doped metal oxide layer formation cycle Q times. At least one of the values K and Q is an integer of 2 or more. K and Q are integers ranging from 1 to about 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, and then injecting an oxide gas into the reactor. The silicon-doped metal oxide layer formation cycle includes supplying a metal source gas including silicon into a reactor containing the substrate, and then injecting an oxide gas into the reactor.
    Type: Application
    Filed: January 11, 2006
    Publication date: November 16, 2006
    Inventors: Seok-Joo Doh, Shi-Woo Rhee, Jong-Pyo Kim, Jung-Hyoung Lee, Jong-Ho Lee, Yun-Seok Kim
  • Publication number: 20060157750
    Abstract: Provided is a semiconductor device having an etch-resistant L-shaped spacer and a fabrication method thereof. The semiconductor device comprises a semiconductor substrate, a gate insulating layer formed on the semiconductor substrate, a gate electrode formed on the gate insulating layer, an L-shaped lower spacer conformally formed on sidewalls of the gate electrode and a portion of the substrate, an etch-resistant L-shaped spacer conformally formed on the L-shaped lower spacer, low-concentration source/drain regions aligned to sides of sidewall portions of the L-shaped lower spacer and formed within the substrate, and high-concentration source/drain regions aligned to sides of a bottom portions of the etch-resistant L-shaped spacer and formed within the substrate.
    Type: Application
    Filed: June 30, 2005
    Publication date: July 20, 2006
    Inventors: Jong-pyo Kim, Young-gun Ko, Jong-ho Yang
  • Patent number: 7041990
    Abstract: An input parameter monitoring apparatus is disclosed wherein input parameters for ion implantation can be stored in a database during an ion implantation process, thereby allowing a user to monitor the operational history from a remote location. A method of monitoring input parameters created during an ion implantation process in a semiconductor fabricating device includes collecting log data generated by a plurality of ion implantation devices, listing the collected log data in a database in chronological order and updating the database substantially contemporaneously during said process. The log data can be processed to enable textual or graphical display. A LAN connects a local computer connected via input ports to plural ion-imp devices and a remote computer, thereby enabling remote computer monitoring of the operational process and possibly interaction.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: May 9, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Pyo Kim, Mun-Hee Lee
  • Publication number: 20060054980
    Abstract: A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric layer which is formed on top of the lower dielectric layer and which is made of amorphous metal oxide (M?Oy) or amorphous metal oxynitride (M?OyNz).
    Type: Application
    Filed: September 13, 2005
    Publication date: March 16, 2006
    Inventors: Jong-Pyo Kim, Jong-Ho Lee, Hyung-Suk Jung, Jung-Hyoung Lee
  • Publication number: 20060022252
    Abstract: There are provided a nonvolatile memory device and a method of fabricating the same. A gate region of the nonvolatile memory device is formed as a stack structure including a tunnel oxide layer, a trapping layer, a blocking layer and a control gate electrode. The trapping layer is formed of a high-k dielectric having a higher dielectric constant than that of the tunnel oxide layer. When the trapping layer is formed of high-k dielectric, an EOT in a same thickness can be reduced, and excitation of electrons of the control gate electrode to the tunnel oxide layer due to a high potential barrier relative to the tunnel oxide layer is prevented so that program and erase voltages can be further reduced. As such, a problem that the tunnel oxide layer is damaged due to the conventional high program and erase voltages can be solved by reducing the program and erase voltages, and program and erase speeds of the transistor can be further improved.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 2, 2006
    Inventors: Seok-Joo Doh, Jong-Pyo Kim, Jong-Ho Lee, Ki-Chul Kim
  • Publication number: 20050255246
    Abstract: There are provided methods of fabricating a metal silicate layer on a semiconductor substrate using an atomic layer deposition technique. The methods include performing a metal silicate layer formation cycle at least one time in order to form a metal silicate layer having a desired thickness. The metal silicate layer formation cycle includes an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon oxide layer formation cycle Q times. K and Q are integers ranging from 1 to 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, exhausting the metal source gas remaining in a reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor.
    Type: Application
    Filed: May 12, 2005
    Publication date: November 17, 2005
    Inventors: Yun-Seok Kim, Jong-Pyo Kim, Ha-Jin Lim, Jae-Eun Park, Hyung-Suk Jung, Jong-Ho Lee, Jong-Ho Yang
  • Publication number: 20050156256
    Abstract: Methods of fabricating a lanthanum oxide layer, and methods of fabricating a MOSFET and/or a capacitor especially adapted for semiconductor applications using such a lanthanum oxide layer are disclosed. The methods include a preliminary step of disposing a semiconductor substrate into a chamber. Tris(bis(trimethylsilyl)amino)Lanthanum as a lanthanum precursor is then injected into the chamber such that the lanthanum precursor is chemisorbed on the semiconductor substrate. Then, after carrying out a first purge of the chamber, at least one oxidizer is injected into the chamber such that the oxidizer is chemisorbed with the lanthanum precursor on the semiconductor substrate. Then, the chamber is purged a second time.
    Type: Application
    Filed: January 12, 2005
    Publication date: July 21, 2005
    Inventors: Jong-Pyo Kim, Jung-Hyun Lee, Bum-Seok Seo, Jung-Hyoung Lee
  • Publication number: 20030001111
    Abstract: An input parameter monitoring apparatus is disclosed wherein input parameters for ion implantation can be stored in a database during an ion implantation process, thereby allowing a user to monitor the operational history from a remote location. A method of monitoring input parameters created during an ion implantation process in a semiconductor fabricating device includes collecting log data generated by a plurality of ion implantation devices, listing the collected log data in a database in chronological order and updating the database substantially contemporaneously during said process. The log data can be processed to enable textual or graphical display. A LAN connects a local computer connected via input ports to plural ion-imp devices and a remote computer, thereby enabling remote computer monitoring of the operational process and possibly interaction.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 2, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong-Pyo Kim, Mun-Hee Lee