Patents by Inventor Jong-Seo Hong
Jong-Seo Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9989856Abstract: Disclosed is a method of manufacturing semiconductor devices. A dummy gate structure is formed on a pattern area defined by an edge area of a substrate. An interlayer insulating layer pattern is formed to cover the pattern area and exposing the edge area of the substrate. A blocking pattern is formed on the interlayer insulating layer pattern such that the edge area of the substrate is covered with the blocking pattern and the pattern area of the substrate is exposed through the blocking pattern. A gate hole in the pattern area of the substrate in correspondence to the dummy gate structure, and a metal gate structure is formed in the gate hole. Accordingly, the edge area of the substrate is protected in the etching process and the deposition process of the replacement gate metal (RGM) process.Type: GrantFiled: March 25, 2016Date of Patent: June 5, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Woo Seo, Sang-Jin Kim, Jong-Seo Hong, Jong-Hoon Nah, Choon-Ho Song
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Patent number: 9859175Abstract: Provided are substrate processing systems and methods of managing the same. The method may include displaying a notification for a preventive maintenance operation on a chamber, performing a maintenance operation on the chamber, performing a first optical test, and evaluating the preventive maintenance operation. The first optical test may include generating a reference plasma reaction, measuring a variation of intensity by wavelength for plasma light emitted from the reference plasma reaction, and calculating an electron density and an electron temperature from a ratio in intensity of the plasma light.Type: GrantFiled: April 29, 2016Date of Patent: January 2, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kiwook Song, Bum-Soo Kim, Kye Hyun Baek, Masayuki Tomoyasu, Eunwoo Lee, Jong Seo Hong
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Publication number: 20170047200Abstract: A plasma processing apparatus includes a chamber defining a process space, an upper electrode mounted in the chamber, the upper electrode including a first gas spray port located in a central region of the upper electrode and a second gas spray port located in a peripheral region of the upper electrode, a lower electrode located opposite the upper electrode across the process space, a first gas supply unit configured to supply a first process gas into the process space via the first gas spray port and the second gas spray port, a second gas supply unit configured to supply a second process gas into the process space via the second gas spray port, a sensor configured to sense a state of plasma in an edge portion of the process space, and a controller configured to control the second gas supply unit in response to an output signal of the sensor.Type: ApplicationFiled: April 13, 2016Publication date: February 16, 2017Inventors: Hyung-Joo Lee, Kye-hyun Baek, Masayuki Tomoyasu, Jong-seo Hong, Jin-pyoung Kim
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Publication number: 20170032987Abstract: Disclosed are a dry etching apparatus and a method of etching a substrate using the same. The apparatus includes a base at a lower portion of process chamber in which a dry etching process is performed, a substrate holder arranged on the base and holding a substrate on which a plurality of pattern structures is formed by the etching process, a focus ring enclosing the substrate holder and uniformly focusing an etching plasma to a sheath area over the substrate, a driver driving the focus ring in a vertical direction perpendicular to the base and a position controller controlling a vertical position of the focus ring by selectively driving the driver in accordance with inspection results of the pattern structures. Accordingly, the gap distance between the substrate and the focus ring is automatically controlled to thereby increase the uniformity of the etching plasma over the substrate.Type: ApplicationFiled: April 12, 2016Publication date: February 2, 2017Inventors: Hyung-Joo LEE, Kwang-Nam KIM, Jong-Seo HONG, Kye-Hyun BAEK, Masayuki TOMOYASU
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Publication number: 20160372386Abstract: Provided are substrate processing systems and methods of managing the same. The method may include displaying a notification for a preventive maintenance operation on a chamber, performing a maintenance operation on the chamber, performing a first optical test, and evaluating the preventive maintenance operation. The first optical test may include generating a reference plasma reaction, measuring a variation of intensity by wavelength for plasma light emitted from the reference plasma reaction, and calculating an electron density and an electron temperature from a ratio in intensity of the plasma light.Type: ApplicationFiled: April 29, 2016Publication date: December 22, 2016Inventors: Kiwook SONG, Bum-Soo KIM, Kye Hyun BAEK, MASAYUKI TOMOYASU, Eunwoo LEE, JONG SEO HONG
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Publication number: 20160293728Abstract: Disclosed is a method of manufacturing semiconductor devices. A dummy gate structure is formed on a pattern area defined by an edge area of a substrate. An interlayer insulating layer pattern is formed to cover the pattern area and exposing the edge area of the substrate. A blocking pattern is formed on the interlayer insulating layer pattern such that the edge area of the substrate is covered with the blocking pattern and the pattern area of the substrate is exposed through the blocking pattern. A gate hole in the pattern area of the substrate in correspondence to the dummy gate structure, and a metal gate structure is formed in the gate hole. Accordingly, the edge area of the substrate is protected in the etching process and the deposition process of the replacement gate metal (RGM) process.Type: ApplicationFiled: March 25, 2016Publication date: October 6, 2016Inventors: Jung-Woo SEO, Sang-Jin KIM, Jong-Seo HONG, Jong-Hoon NAH, Choon-Ho SONG
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Patent number: 9299811Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.Type: GrantFiled: October 21, 2014Date of Patent: March 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Wook-Je Kim, Jae-Yup Chung, Jong-Seo Hong, Cheol Kim, Hee-Soo Kang, Hyun-Jo Kim, Hee-Don Jeong, Soo-Hun Hong, Sang-Bom Kang, Myeong-Cheol Kim, Young-Su Chung
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Publication number: 20150147860Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.Type: ApplicationFiled: October 21, 2014Publication date: May 28, 2015Inventors: Wook-Je Kim, Jae-Yup Chung, Jong-Seo Hong, Cheol Kim, Hee-Soo Kang, Hyun-Jo Kim, Hee-Don Jeong, Soo-Hun Hong, Sang-Bom Kang, Myeong-Cheol Kim, Young-Su Chung
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Publication number: 20150076617Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.Type: ApplicationFiled: November 20, 2014Publication date: March 19, 2015Inventors: Myeong-Cheol Kim, Il-Sup Kim, Cheol Kim, Jong-Chan Shin, Jong-Wook Lee, Choong-Ho Lee, Si-Young Choi, Jong-Seo Hong
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Patent number: 8906757Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.Type: GrantFiled: November 12, 2012Date of Patent: December 9, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong-Cheol Kim, Il-Sup Kim, Cheol Kim, Jong-Chan Shin, Jong-Wook Lee, Choong-Ho Lee, Si-Young Choi, Jong-Seo Hong
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Patent number: 8569140Abstract: A method for fabricating a semiconductor device is disclosed. One embodiment of the method includes forming a dummy gate pattern on a substrate, forming an interlayer dielectric film that covers the dummy gate pattern, exposing a top surface of the dummy gate pattern, selectively removing the dummy gate pattern to form a first gate trench, forming a sacrificial layer pattern over a top surface of the substrate in the first gate trench, the sacrificial layer pattern leaving a top portion of the first gate trench exposed, increasing an upper width of the exposed top portion of the first gate trench to form a second gate trench, and removing the sacrificial layer pattern in the second gate trench, and forming a non-dummy gate pattern in the second gate trench.Type: GrantFiled: July 29, 2011Date of Patent: October 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Tae Kim, Jong-Seo Hong, Tae-Han Kim
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Patent number: 8563412Abstract: A method of fabricating a semiconductor device includes forming gate patterns on a substrate, forming spacers on sidewalls of the gate patterns, forming a first capping insulation layer pattern on the gate patterns and the spacers, forming a second capping insulation layer pattern on the first capping insulation layer pattern, forming a passivation layer pattern filling contact holes between the gate patterns, removing the second capping insulation layer pattern while protecting the spacers using the passivation layer pattern, removing the passivation layer pattern to expose a top surface of the substrate, forming a silicide forming metal film on the surface of the substrate, and forming silicide patterns on the exposed top surface of the substrate.Type: GrantFiled: August 8, 2011Date of Patent: October 22, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Tae Kim, Jong-Seo Hong
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Patent number: 8394697Abstract: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.Type: GrantFiled: January 20, 2011Date of Patent: March 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Seo Hong, Jeong-Sic Jeon, Chun-Suk Suh, Yoo-Sang Hwang
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Publication number: 20120052667Abstract: A method of fabricating a semiconductor device includes forming gate patterns on a substrate, forming spacers on sidewalls of the gate patterns, forming a first capping insulation layer pattern on the gate patterns and the spacers, forming a second capping insulation layer pattern on the first capping insulation layer pattern, forming a passivation layer pattern filling contact holes between the gate patterns, removing the second capping insulation layer pattern while protecting the spacers using the passivation layer pattern, removing the passivation layer pattern to expose a top surface of the substrate, forming a silicide forming metal film on the surface of the substrate, and forming silicide patterns on the exposed top surface of the substrate.Type: ApplicationFiled: August 8, 2011Publication date: March 1, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyu-Tae Kim, Jong-Seo Hong
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Publication number: 20120052647Abstract: A method for fabricating a semiconductor device is disclosed. One embodiment of the method includes forming a dummy gate pattern on a substrate, forming an interlayer dielectric film that covers the dummy gate pattern, exposing a top surface of the dummy gate pattern, selectively removing the dummy gate pattern to form a first gate trench, forming a sacrificial layer pattern over a top surface of the substrate in the first gate trench, the sacrificial layer pattern leaving a top portion of the first gate trench exposed, increasing an upper width of the exposed top portion of the first gate trench to form a second gate trench, and removing the sacrificial layer pattern in the second gate trench, and forming a non-dummy gate pattern in the second gate trench.Type: ApplicationFiled: July 29, 2011Publication date: March 1, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyu-Tae Kim, Jong-Seo Hong, Tae-Han Kim
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Publication number: 20110117715Abstract: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.Type: ApplicationFiled: January 20, 2011Publication date: May 19, 2011Inventors: Jong-Seo Hong, Jeong-Sic Jeon, Chun-Suk Suh, Yoo-Sang Hwang
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Patent number: 7888724Abstract: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.Type: GrantFiled: December 22, 2005Date of Patent: February 15, 2011Assignee: Samsung Electronics, Co., Ltd.Inventors: Jong-Seo Hong, Jeong-Sic Jeon, Chun-Suk Suh, Yoo-Sang Hwang
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Patent number: 7851354Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.Type: GrantFiled: November 10, 2008Date of Patent: December 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-woo Seo, Jong-seo Hong, Tae-hyuk Ahn, Jeong-sic Jeon, Jun-sik Hong, Young-sun Cho
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Patent number: 7682778Abstract: Provided are contact photomasks and methods using such photomasks for fabricating semiconductor devices and forming contact plugs on portions of active regions exposed between gate lines. The elongated active regions are arrayed in a series of parallel groups with each group being, in turn, aligned along their longitudinal axes to form an acute angle with the gate lines. The contact photomask includes a plurality of openings arranged in parallel lines that are aligned at an angle offset from previously formed gate lines and which may be parallel to the active regions or may be aligned at an angle offset from the axes of both the groups of active regions and the gate lines. Processes for forming contact plugs using such photomasks may provide increased processing margin and extend the utility of conventional exposure equipment for semiconductor devices exhibiting increased integration density and/or built to more demanding design rules.Type: GrantFiled: January 31, 2006Date of Patent: March 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Woo Seo, Tae-Hyuk Ahn, Jong-Seo Hong
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Patent number: 7648875Abstract: A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the top of the bitline. A protective layer is formed an entire surface of the resultant structure. A sacrificial layer is formed on the protective layer. The sacrificial layer, the protective layer, and the second interlayer dielectric are patterned between two adjacent bitlines to form a bottom electrode contact hole exposing the contact pad. A conductive layer is formed and planarized to form a bottom electrode contact plug filling the bottom electrode contact hole.Type: GrantFiled: January 6, 2006Date of Patent: January 19, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Seo Hong, Jung-Woo Seo, Jun-Sik Hong, Jeong-Sic Jeon