Abstract: Therapeutic compounds for red blood cell-mediated delivery of an active pharmaceutical ingredient to a target cell are described. The therapeutic compounds are configured to bind CD47 on the surface of a red blood cell and to be subsequently transferred to CD47 on the surface of the target cell, the therapeutic compound ultimately being internalized by the target cell via endocytosis. The target cell may be a fibrotic cell.

Abstract: A semiconductor device includes a first Low Noise Amplifier (LNA), a second LNA, first and second receiving circuits, an a radio frequency multiplexer. The first LNA is connected to a first receiving port, and the second LNA is connected to a second receiving port different from the first receiving port. The first receiving circuit includes a first transformer and processes one or more outputs of the first and second LNAs. The second receiving circuit processes one or more of the outputs of the first and second LNAs. The radio frequency multiplexer controls connection between the first and second LNAs and the first and second receiving circuits. The first receiving circuit includes a first variable capacitor having a first end connected to an output of the radio frequency multiplexer and a second end connected to the first transformer.

Abstract: An audio segmentation method based on an attention mechanism is provided. The audio segmentation method according to an embodiment obtains a mapping relationship between an “inputted text” and an “audio spectrum feature vector for generating an audio signal”, the audio spectrum feature vector being automatically synthesized by using the inputted text, and segments an inputted audio signal by using the mapping relationship. Accordingly, high quality can be guaranteed and the effort, time, and cost can be noticeably reduced through audio segmentation utilizing the attention mechanism.

Abstract: An audio synthesis method adapted to video characteristics is provided. The audio synthesis method according to an embodiment includes: extracting characteristics x from a video in a time-series way; extracting characteristics p of phonemes from a text; and generating an audio spectrum characteristic St used to generate an audio to be synthesized with a video at a time t, based on correlations between an audio spectrum characteristic St-1, which is used to generate an audio to be synthesized with a video at a time t?1, and the characteristics x. Accordingly, an audio can be synthesized according to video characteristics, and speech according to a video can be easily added.

Abstract: An audio synthesis method adapted to video characteristics is provided. The audio synthesis method according to an embodiment includes: extracting characteristics x from a video in a time-series way; extracting characteristics p of phonemes from a text; and generating an audio spectrum characteristic St used to generate an audio to be synthesized with a video at a time t, based on correlations between an audio spectrum characteristic St-1, which is used to generate an audio to be synthesized with a video at a time t?1, and the characteristics x. Accordingly, an audio can be synthesized according to video characteristics, and speech according to a video can be easily added.

Abstract: An audio segmentation method based on an attention mechanism is provided. The audio segmentation method according to an embodiment obtains a mapping relationship between an “inputted text” and an “audio spectrum feature vector for generating an audio signal”, the audio spectrum feature vector being automatically synthesized by using the inputted text, and segments an inputted audio signal by using the mapping relationship. Accordingly, high quality can be guaranteed and the effort, time, and cost can be noticeably reduced through audio segmentation utilizing the attention mechanism.

Abstract: A fuse circuit may include a plurality of first fuse sets and a plurality of second fuse sets. The plurality of first fuse sets may be used to store a defect address detected before packaging of a semiconductor apparatus. The plurality of second fuse sets may be used to store a defect address detected after the packaging. The plurality of first fuse sets may be shared by a plurality of first redundant word lines, and the plurality of second fuse sets may be in one-to-one correspondence with a plurality of second redundant word lines.

Abstract: A memory device may include a command controller configured to buffer an address based on a refresh enable signal and a repair enable signal. The memory device may include a fuse circuit configured to control a rupture operation of a refresh cell array and repair cell array corresponding to the address according to the refresh enable signal and the repair enable signal, and output a refresh control signal and a repair control signal during a boot-up operation. The memory device may include a refresh controller configured to control a refresh operation of a bank according to a refresh control signal. The memory device may include a repair controller configured to control a repair operation of the bank according to a redundancy signal.

Abstract: An embodiment relates to a power control device and a technology capable of stably supplying power when an electrical fuse boots up. The power control device includes a power supply unit, a power driving unit, and an electrical fuse unit. The power supply unit generates a driving signal from a power supply voltage when a control signal is activated. The power driving unit outputs the driving signal when the control signal is activated. The electrical fuse unit generates, when a boot-up enable signal is activated, a clock signal by performing a boot-up operation in response to the driving signal outputted from the power driving unit.

Abstract: A fuse circuit may include a plurality of first fuse sets and a plurality of second fuse sets. The plurality of first fuse sets may be used to store a defect address detected before packaging of a semiconductor apparatus. The plurality of second fuse sets may be used to store a defect address detected after the packaging. The plurality of first fuse sets may be shared by a plurality of first redundant word lines, and the plurality of second fuse sets may be in one-to-one correspondence with a plurality of second redundant word lines.

Abstract: A memory device may include a command controller configured to buffer an address based on a refresh enable signal and a repair enable signal. The memory device may include a fuse circuit configured to control a rupture operation of a refresh cell array and repair cell array corresponding to the address according to the refresh enable signal and the repair enable signal, and output a refresh control signal and a repair control signal during a boot-up operation. The memory device may include a refresh controller configured to control a refresh operation of a bank according to a refresh control signal. The memory device may include a repair controller configured to control a repair operation of the bank according to a redundancy signal.

Abstract: An embodiment relates to a power control device and a technology capable of stably supplying power when an electrical fuse boots up. The power control device includes a power supply unit, a power driving unit, and an electrical fuse unit. The power supply unit generates a driving signal from a power supply voltage when a control signal is activated. The power driving unit outputs the driving signal when the control signal is activated. The electrical fuse unit generates, when a boot-up enable signal is activated, a clock signal to by performing a boot-up operation in response to the driving signal outputted from the power driving unit.

Abstract: A semiconductor device includes a memory cell array including a normal memory cell array and a redundancy memory cell array, a normal refresh counter suitable for generating a normal address for performing a refresh operation to the normal memory cell array with a first period during a refresh mode and a redundancy refresh counter suitable for generating a redundancy address for performing a refresh operation to the redundancy memory cell with a second period shorter than the first period.

Abstract: A memory device includes: a non-volatile memory circuit suitable for storing hard repair data; a data bus suitable for transmitting the hard repair data during a boot-up operation, and transmitting soft repair data during a soft repair mode; a plurality of registers suitable for storing repair data transmitted through the data bus and activated when the transmitted repair data is stored; a control circuit suitable for selecting a register to store the transmitted repair data among the plurality of the registers, and during the soft repair mode, deactivating a register that stores the same data as the transmitted repair data; and a memory bank suitable for performing a repair operation based on the data stored in a register that is activated among the plurality of the registers.

Abstract: A semiconductor memory device includes a refresh cycle generation unit capable of generating a first cycle signal and a second cycle signal having a cycle shorter than the first cycle signal; and a refresh control unit capable of generating a plurality of row addresses based on the first or second cycle signal.

Abstract: A memory device may include an address latch circuit that latches an address received from an exterior of the memory device, a repair signal generation circuit that generates a soft repair signal, a selection information generation circuit that generates first selection information by using first bits of a latched address latched by the address latch circuit, first to Nth register circuits that store second bits of the latched address as repair data by being selected by the first selection information when the soft repair signal is activated, and first to Nth memory blocks that perform repair operations using the repair data stored in the respective first to Nth register circuits.

Abstract: A memory device comprises a cell array having a plurality of word lines, an address counting unit suitable for generating a counting address that is changed whenever one or more of the plurality of word lines are refreshed, and a control unit suitable for selecting a word line corresponding to the counting address among the plurality of word lines and refreshing the selected word line within a first period in response to a refresh command during a first operation mode, within a second period that is longer than the first period during a second operation mode, and within a third period that is shorter than the second period in a high frequency section after the second operation mode begins.

Abstract: A memory device may include an address latch circuit that latches an address received from an exterior of the memory device, a repair signal generation circuit that generates a soft repair signal, a selection information generation circuit that generates first selection information by using first bits of a latched address latched by the address latch circuit, first to Nth register circuits that store second bits of the latched address as repair data by being selected by the first selection information when the soft repair signal is activated, and first to Nth memory blocks that perform repair operations using the repair data stored in the respective first to Nth register circuits.

Abstract: A memory device includes: a non-volatile memory circuit suitable for storing hard repair data; a data bus suitable for transmitting the hard repair data during a boot-up operation, and transmitting soft repair data during a soft repair mode; a plurality of registers suitable for storing repair data transmitted through the data bus and activated when the transmitted repair data is stored; a control circuit suitable for selecting a register to store the transmitted repair data among the plurality of the registers, and during the soft repair mode, deactivating a register that stores the same data as the transmitted repair data; and a memory bank suitable for performing a repair operation based on the data stored in a register that is activated among the plurality of the registers.

Abstract: A semiconductor memory apparatus includes a sense amplifier driving control unit configured to be applied with first and second driving voltages, and generate first to third sense amplifier driving signals in response to a mat enable signal, a sense amplifier enable signal and a power-up signal; a sense amplifier driving unit configured to, in response to the first to third sense amplifier driving signals, connect first and second sense amplifier driving nodes to cause the first and second sense amplifier driving nodes to have substantially the same voltage level, or disconnect the first and second sense amplifier driving nodes to apply first and second sense amplifier driving voltages to the first and second sense amplifier driving nodes; and a sense amplifier configured to be applied with the first and second sense amplifier driving voltages, and sense and amplify a voltage difference of a bit line and a bit line bar.