Patents by Inventor Joo-Chan Kim

Joo-Chan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10686172
    Abstract: The present invention provides a battery module assembly including: a module array body including two or more unit modules, each including a plurality of battery cells, the unit modules being arranged while sides thereof are closely attached to each other; and a combination-type module housing that includes a first space set by combining a plurality of plate members, and a second space set in the first space while a fixing bracket is additionally combined to one of the plurality of plate members.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: June 16, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Hyoung Suk Lee, Na Ri Shin, Joo Sung Kim, Hyun Chan Kim
  • Patent number: 10660605
    Abstract: An image processing module includes a beamforming unit configured to provide a beamformed signal based on an input signal; a point spread function (PSF) database comprising at least one two-dimensional point spread function obtained based on at least one situational variable of the beamformed signal; and an image generation unit configured to select at least one two-dimensional point spread function from the point spread function database and perform deconvolution using the beamformed signal and the selected at least one two-dimensional point spread function to generate an image of a target portion of an object.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joo Young Kang, Sung Chan Park, Kyu Hong Kim, Jung Ho Kim
  • Patent number: 10665832
    Abstract: The present invention relates to a battery pack including: a plurality of battery modules each including a plurality of battery cells, wherein at least one of the battery modules has a layer structure with the remaining battery modules based on the ground; a battery management system (BMS) mounted adjacent to the battery modules and monitoring and controlling operation of the battery modules; a battery disconnect unit (BDU) mounted adjacent to the battery modules and controlling electrical connection of the battery modules; a base plate having a structure in which the battery modules are mounted on an upper surface thereof and a lower end part thereof is fixed to an external device; and a pack cover surrounding the battery modules and coupled to an outer periphery of the base plate.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 26, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Hyun Chan Kim, Joo Sung Kim, Na Ri Shin
  • Patent number: 10646204
    Abstract: A medical image processing apparatus includes a weight applier configured to, when a difference between a first imaginary component of a first frame image and a second imaginary component of a second frame image, the second frame image being adjacent to the first frame image, is less than or equal to a first threshold value, apply a first weight to the second imaginary component to increase the difference; and an image generator configured to generate a movement-amplified image based on the first frame image and the second frame image to which the first weight is applied so that a movement of interest corresponding to the increased difference is amplified.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Young Kang, Kyu Hong Kim, Bae Hyung Kim, Su Hyun Park, Young Ihn Kho, Jung Ho Kim, Sung Chan Park
  • Patent number: 10622602
    Abstract: The present invention relates to a battery pack including: a plurality of battery modules each including a plurality of battery cells, wherein at least one of the battery modules has a layer structure with the remaining battery modules based on the ground; a battery management system (BMS) mounted adjacent to the battery modules and monitoring and controlling operation of the battery modules; a battery disconnect unit (BDU) mounted adjacent to the battery modules and controlling electrical connection of the battery modules; a base plate having a structure in which the battery modules are mounted on an upper surface thereof and a lower end part thereof is fixed to an external device; and a pack cover surrounding the battery modules and coupled to an outer periphery of the base plate.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: April 14, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Hyun Chan Kim, Joo Sung Kim, Na Ri Shin
  • Publication number: 20200105854
    Abstract: An organic light emitting diode (OLED) display includes a first electrode, a pixel defining layer that at least partially exposes the first electrode, an organic light emitting layer on the first electrode, a thin-film encapsulation layer on the organic light emitting layer, and a light shielding member on the thin-film encapsulation the light shielding member overlapping the pixel defining layer. The organic light emitting layer includes a main area not overlapping the pixel defining layer and a sub area overlapping the pixel defining layer. The main area includes an open portion not overlapping the light shielding member and a shadow portion around the open portion overlapping the light shielding member.
    Type: Application
    Filed: August 23, 2019
    Publication date: April 2, 2020
    Inventors: Gun Hee KIM, Sang Ho PARK, Ju Won YOON, Seung Chan LEE, Joo Hee JEON
  • Publication number: 20200051966
    Abstract: A display device and a method for fabricating the same. The display device includes a substrate including a circuit layer and a first pad unit; an auxiliary substrate disposed below the substrate and comprising a driving circuit and a second pad unit; a light-emitting unit disposed on the circuit layer; and a connection electrode in contact with a side surface of the substrate and electrically connecting the first pad unit with the second pad unit. The method includes forming a circuit layer and a first pad unit on a first surface of a substrate; forming a driving circuit and a second pad unit on a fourth surface of an auxiliary substrate; and attaching a second surface of the substrate opposite the first surface to a third surface of the auxiliary substrate opposite the fourth surface.
    Type: Application
    Filed: April 2, 2019
    Publication date: February 13, 2020
    Inventors: Seung Chan Lee, Gun Hee Kim, Sang Ho Park, Ju Won Yoon, Joo Hee Jeon, Hyun Joon Kim
  • Patent number: 10465098
    Abstract: The present invention provides an optical adhesive sheet including a layered structure of a first adhesive layer and a second adhesive layer, in which the first adhesive layer has a glass transition temperature of ?50° C. to ?30° C. and a modulus of 0.3×105 Pa to about 0.6×105 Pa, and the second adhesive layer has a glass transition temperature of ?20° C. to ?10° C. and a modulus of 0.7×105 Pa to 1.0×105 Pa.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: November 5, 2019
    Assignee: LG Chem, Ltd.
    Inventors: Joo-Hyun Lee, Jang-Soon Kim, Bu-Gi Jung, Sang-Hwan Kim, Sung-Chan Park, Chan-Oh Yoon, Han-Na Lee
  • Patent number: 10426436
    Abstract: An ultrasonic probe includes a multi-dimensionally arrayed transducer, a matching layer, and a backing layer. The transducer includes element groups having different focal distances and simultaneously transmitting ultrasonic signals toward an object. According to the ultrasonic imaging apparatus using the multi-dimensionally arrayed transducer, a multi-focus transmission is performed. Thus, the multi-focus ultrasonic image may be acquired within a short period of time, thereby increasing frame rates, and a high-quality image in which all areas are focused may be quickly acquired.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joo Young Kang, Sung Chan Park, Kyu Hong Kim, Jung Ho Kim, Su Hyun Park
  • Patent number: 10359509
    Abstract: Disclosed herein are an image processor, an ultrasonic imaging device, and an image processing method. The image processor includes a signal input unit configured to receive an input signal on a channel, a weighting coefficient database configured to store a weighting coefficient wherein the weighting coefficient is part of a weighting coefficient subgroup, and a processor configured to select the weighting coefficient subgroup from the weighting coefficient database, and convert the input signal by selecting and using the weighting coefficient from the weighting coefficient subgroup.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu Hong Kim, Sung Chan Park, Su Hyun Park, Joo Young Kang, Jung Ho Kim
  • Publication number: 20190173064
    Abstract: The present invention provides a battery module assembly including: a module array body including two or more unit modules, each including a plurality of battery cells, the unit modules being arranged while sides thereof are closely attached to each other; and a combination-type module housing that includes a first space set by combining a plurality of plate members, and a second space set in the first space while a fixing bracket is additionally combined to one of the plurality of plate members.
    Type: Application
    Filed: January 11, 2017
    Publication date: June 6, 2019
    Applicant: LG CHEM, LTD.
    Inventors: Hyoung Suk LEE, Na Ri SHIN, Joo Sung KIM, Hyun Chan KIM
  • Patent number: 10298045
    Abstract: A method of controlling an electronic device is provided which includes electrically connecting a battery with an external power source using a first switch such that a first portion of a first current supplied from the external power source is supplied to a system circuit of the electronic device and a second portion of the first current is supplied to the battery, determining whether a specified condition is satisfied, electrically disconnecting the battery from the external power source using the first switch and electrically connecting the battery with a resistor using a second switch, if the specified condition is satisfied, verifying an electrical characteristic of a current applied to the resistor while the battery is electrically disconnected from the external power source and is electrically connected with the resistor, and determining whether an operation of the battery is abnormal, based at least on a part of the electrical characteristic.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hoon Jung, Joo Hoan Do, Min Woo Song, Sung Won Moon, Hyun Seok Lee, Eui Chan Jung, Moo Young Kim, Hyo Seok Na, Ji Woo Lee
  • Patent number: 8288825
    Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: October 16, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Joo Chan Kim, Judson Robert Holt
  • Patent number: 7939413
    Abstract: An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: May 10, 2011
    Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Joo Chan Kim, Brian Joseph Greene, Kern Rim
  • Patent number: 7838390
    Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: November 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo
  • Publication number: 20100219485
    Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.
    Type: Application
    Filed: May 17, 2010
    Publication date: September 2, 2010
    Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO. LTD
    Inventors: Yung Fu CHONG, Zhijiong LUO, Joo Chan KIM, Judson Robert HOLT
  • Publication number: 20100171182
    Abstract: A strained semiconductor device includes a first plurality of transistors spaced with a first gate pitch, a second plurality of transistors spaced with a second gate pitch greater than the first gate pitch, and an etch stop layer disposed on the first and second pluralities of transistors. The etch stop layer between each of the second plurality of transistors has a greater proportion of a stress-altering material than the etch stop layer between each of the first plurality of transistors.
    Type: Application
    Filed: January 5, 2010
    Publication date: July 8, 2010
    Inventors: Dong-Suk Shin, Pan-Kwi Park, Ha-Jin Lim, Joo-Chan Kim
  • Patent number: 7718500
    Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: May 18, 2010
    Assignees: Chartered Semiconductor Manufacturing, Ltd, International Business Machines Corporation (IBM), Samsung Electronics Co., Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Joo Chan Kim, Judson Robert Holt
  • Patent number: 7564092
    Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: July 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eui-youl Ryu, Chul-soon Kwon, Jin-woo Kim, Yong-hee Kim, Dai-geun Kim, Joo-chan Kim
  • Publication number: 20090098706
    Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.
    Type: Application
    Filed: October 12, 2007
    Publication date: April 16, 2009
    Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo