Abstract: A button-type secondary battery includes a lower can having a bottom surface; an upper can having a top, the upper can and the lower can being coupled to define a space therein; an electrolyte in the space; an electrode assembly in the space and including a negative electrode, a separator, and a positive electrode wound together; a gasket between the upper can and the lower can to electrically insulate the upper and lower cans; a top insulator that is electrically insulating and covering a top surface of the electrode assembly; and a bottom insulator that is electrically insulating and covering a bottom surface of the electrode assembly. The top and bottom insulators are each configured to expand in volume by absorbing the electrolyte. Surfaces of at least one of the top insulator and the bottom insulator are coated with a protective layer to prevent thermal shrinkage from occurring.

Abstract: A button type secondary battery includes a wound electrode assembly; a lower can with the electrode assembly and an electrolyte in the lower can; a top plate to close the lower can; a positive electrode terminal coupled to the top plate through a gasket to be electrically insulated from the top plate with a portion of the positive electrode terminal passing through a hole in the top plate to be bonded to a positive electrode tab; a top insulator covering a top surface of the electrode assembly; and a bottom insulator covering a bottom surface of the electrode assembly. The top insulator and the bottom insulator are each configured to expand in volume by absorbing the electrolyte. Surfaces of at least one or more of the top insulator and the bottom insulator are coated with a protective layer configured to prevent thermal shrinkage from occurring.

Abstract: A surface-treated copper foil according to exemplary embodiments includes a copper foil layer and a protrusion layer formed on one surface of the copper foil layer. Pores are formed inside the protrusion layer or around a boundary between the copper foil layer and the protrusion layer. Abnormal growth of the protrusions may be prevented through the pores and thus a bonding force with the insulation layer may be improved.

Abstract: A printed circuit board includes a first insulating layer, a second insulating layer disposed on a lower surface of the first insulating layer, an electronic component embedded in the second insulating layer and at least partially in contact with the first insulating layer, a first wiring layer disposed on an upper surface of the first insulating layer, a second wiring layer disposed on a lower surface of the second insulating layer, and a first wiring via penetrating through the first and second insulating layers and connecting at least portions of the first and second wiring layers to each other.

Abstract: A printed circuit board includes: a first substrate including a first cavity and first circuit units; and a second substrate disposed in the first cavity of the first substrate with an electronic component disposed therein, and including second circuit units having a higher density than the first circuit units, wherein the second substrate includes a first region and a second region, the first region of the second substrate includes an outermost circuit layer among the second circuit units, and circuit layers in the first region of the second substrate have a higher density than circuit layers in the second region of the second substrate.

Abstract: A printed circuit board includes a wiring board including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers, a first die embedded in the plurality of insulating layers, a bridge embedded on the first die in the plurality of insulating layers, a second die mounted on the wiring board, and a third die mounted on the wiring board.

Abstract: A connection structure embedded substrate includes a printed circuit board including a first insulating body and a plurality of first wiring layers disposed on at least one of an external region or an internal region of the first insulating body; and a connection structure embedded in the first insulating body and including first and second substrates. The first and second substrates are disposed adjacent to each other.

Abstract: A semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, and an inductance sensing part having a coil form and electrically connected to the semiconductor chip.

Abstract: A printed circuit board includes a first wiring structure including first insulating layers and first wiring layers; a second wiring structure disposed on the first wiring structure and including second insulating layers and second wiring layers; and a third wiring structure disposed on the second wiring structure and including a third insulating layer and a third wiring layer disposed on the third insulating layer. At least a portion of at least one of the second wiring layers has a fine pitch, relatively finer than those of the first wiring layers and the third wiring layer, wherein at least a portion of one of the first wiring layers is connected to at least a portion of the third wiring layer through a first wiring via, and wherein the first wiring via penetrates at least one of the first insulating layers, the second insulating layers, and the third insulating layer.

Abstract: A connection structure embedded substrate includes a printed circuit board including a first insulating body and a plurality of first wiring layers disposed on at least one of an external region or an internal region of the first insulating body; and a connection structure embedded in the first insulating body and including first and second substrates. The first and second substrates are disposed adjacent to each other.

Abstract: A printed circuit board includes a first insulating layer, a second insulating layer disposed on a lower surface of the first insulating layer, an electronic component embedded in the second insulating layer and at least partially in contact with the first insulating layer, a first wiring layer disposed on an upper surface of the first insulating layer, a second wiring layer disposed on a lower surface of the second insulating layer, and a first wiring via penetrating through the first and second insulating layers and connecting at least portions of the first and second wiring layers to each other.

Abstract: A printed circuit board includes a first wiring structure including first insulating layers and first wiring layers; a second wiring structure disposed on the first wiring structure and including second insulating layers and second wiring layers; and a third wiring structure disposed on the second wiring structure and including a third insulating layer and a third wiring layer disposed on the third insulating layer. At least a portion of at least one of the second wiring layers has a fine pitch, relatively finer than those of the first wiring layers and the third wiring layer, wherein at least a portion of one of the first wiring layers is connected to at least a portion of the third wiring layer through a first wiring via, and wherein the first wiring via penetrates at least one of the first insulating layers, the second insulating layers, and the third insulating layer.

Abstract: A semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, and an inductance sensing part having a coil form and electrically connected to the semiconductor chip.

Abstract: A semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, and an inductance sensing part having a coil form and electrically connected to the semiconductor chip.

Abstract: A fan-out semiconductor package module that is easily manufactured includes a first connection member including a wiring layer, a first passive component mounted on the first connection member, a first encapsulation portion encapsulating at least a portion of the first connection member and the first passive component, a semiconductor chip having an active surface with a connection pad disposed thereon and an inactive surface opposing the active surface and disposed in a first through-hole penetrating through the first connection member and the first encapsulation portion, a second encapsulation portion covering at least a portion of the semiconductor chip and encapsulating at least a portion of the first encapsulation portion and the first connection member, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad and the first passive component.

Abstract: A semiconductor package includes a core member having a cavity penetrating through first and second surfaces, a semiconductor chip disposed in the cavity and having an active surface having connection, a passive component module disposed in the cavity, including a plurality of passive components and a resin portion encapsulating the plurality of passive components, and having a mounting surface from which connection terminals of the passive components are exposed, a connection member on the second surface and including a redistribution layer connected to the connection pads of the semiconductor chip and connection terminals of some of the plurality of passive components, connection terminals of the others of the plurality of passive components not being connected to the redistribution layer.

Abstract: A semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, and an inductance sensing part having a coil form and electrically connected to the semiconductor chip.

Abstract: A fan-out semiconductor package module that is easily manufactured includes a first connection member including a wiring layer, a first passive component mounted on the first connection member, a first encapsulation portion encapsulating at least a portion of the first connection member and the first passive component, a semiconductor chip having an active surface with a connection pad disposed thereon and an inactive surface opposing the active surface and disposed in a first through-hole penetrating through the first connection member and the first encapsulation portion, a second encapsulation portion covering at least a portion of the semiconductor chip and encapsulating at least a portion of the first encapsulation portion and the first connection member, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad and the first passive component.

Abstract: A fan-out semiconductor package module includes: a structure including a wiring member including wiring patterns, one or more first passive components disposed on the wiring member and electrically connected to the wiring pattern, and a first encapsulant encapsulating at least portions of each of the one or more first passive components, and having a first through-hole penetrating through the wiring member and the first encapsulant; a semiconductor chip disposed in the first through-hole of the structure and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; a second encapsulant encapsulating at least portions of the semiconductor chip and filling at least portions of the first through-hole; and a connection member disposed on the structure and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the wiring patterns.

Abstract: A semiconductor package includes a core member having a cavity penetrating through first and second surfaces, a semiconductor chip disposed in the cavity and having an active surface having connection, a passive component module disposed in the cavity, including a plurality of passive components and a resin portion encapsulating the plurality of passive components, and having a mounting surface from which connection terminals of the passive components are exposed, a connection member on the second surface and including a redistribution layer connected to the connection pads of the semiconductor chip and connection terminals of some of the plurality of passive components, connection terminals of the others of the plurality of passive components not being connected to the redistribution layer.