Patents by Inventor Joo Hwan JUNG
Joo Hwan JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10403562Abstract: A fan-out semiconductor package module includes: a structure including a wiring member including wiring patterns, one or more first passive components disposed on the wiring member and electrically connected to the wiring pattern, and a first encapsulant encapsulating at least portions of each of the one or more first passive components, and having a first through-hole penetrating through the wiring member and the first encapsulant; a semiconductor chip disposed in the first through-hole of the structure and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; a second encapsulant encapsulating at least portions of the semiconductor chip and filling at least portions of the first through-hole; and a connection member disposed on the structure and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the wiring patterns.Type: GrantFiled: April 2, 2018Date of Patent: September 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Ho Baek, Joo Hwan Jung, Yoo Rim Cha, Young Sik Hur, Jung Chul Gong
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Publication number: 20190189583Abstract: A semiconductor package includes a core member having a cavity penetrating through first and second surfaces, a semiconductor chip disposed in the cavity and having an active surface having connection, a passive component module disposed in the cavity, including a plurality of passive components and a resin portion encapsulating the plurality of passive components, and having a mounting surface from which connection terminals of the passive components are exposed, a connection member on the second surface and including a redistribution layer connected to the connection pads of the semiconductor chip and connection terminals of some of the plurality of passive components, connection terminals of the others of the plurality of passive components not being connected to the redistribution layer.Type: ApplicationFiled: June 22, 2018Publication date: June 20, 2019Inventors: Yong Ho BAEK, Young Sik HUR, Joo Hwan JUNG
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Patent number: 10283439Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.Type: GrantFiled: June 6, 2018Date of Patent: May 7, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jung Hyun Cho, Yong Ho Baek, Jun Oh Hwang, Joo Hwan Jung, Moon Hee Yi
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Publication number: 20190131212Abstract: A fan-out semiconductor package module includes: a structure including a wiring member including wiring patterns, one or more first passive components disposed on the wiring member and electrically connected to the wiring pattern, and a first encapsulant encapsulating at least portions of each of the one or more first passive components, and having a first through-hole penetrating through the wiring member and the first encapsulant; a semiconductor chip disposed in the first through-hole of the structure and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; a second encapsulant encapsulating at least portions of the semiconductor chip and filling at least portions of the first through-hole; and a connection member disposed on the structure and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the wiring patterns.Type: ApplicationFiled: April 2, 2018Publication date: May 2, 2019Inventors: Yong Ho BAEK, Joo Hwan JUNG, Yoo Rim CHA, Young Sik HUR, Jung Chul GONG
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Patent number: 10242973Abstract: A fan-out semiconductor package module includes: a core member having a first through hole and a second through hole; a semiconductor chip disposed in the first through hole, and having an active surface and an inactive surface opposite the active surface, the active surface having a connection pad disposed thereon; at least one first passive component disposed in the second through hole; a first encapsulant encapsulating the core member encapsulating at least a portion of each of the core member and the at least one first passive component; a second encapsulant encapsulating at least a portion of the inactive surface of the semiconductor chip; and a connection member disposed on the core member, the active surface of the semiconductor chip, and the at least one first passive component, and including a redistribution layer electrically connected to the connection pad and the at least one first passive component.Type: GrantFiled: January 29, 2018Date of Patent: March 26, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yong Ho Baek, Joo Hwan Jung, Young Sik Hur, Jung Chul Gong, Han Kim
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Patent number: 10199329Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.Type: GrantFiled: October 31, 2017Date of Patent: February 5, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Moon Hee Yi, Joo Hwan Jung, Yul Kyo Chung
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Publication number: 20190013300Abstract: A fan-out semiconductor package module includes: a core member having a first through hole and a second through hole; a semiconductor chip disposed in the first through hole, and having an active surface and an inactive surface opposite the active surface, the active surface having a connection pad disposed thereon; at least one first passive component disposed in the second through hole; a first encapsulant encapsulating the core member encapsulating at least a portion of each of the core member and the at least one first passive component; a second encapsulant encapsulating at least a portion of the inactive surface of the semiconductor chip; and a connection member disposed on the core member, the active surface of the semiconductor chip, and the at least one first passive component, and including a redistribution layer electrically connected to the connection pad and the at least one first passive component.Type: ApplicationFiled: January 29, 2018Publication date: January 10, 2019Inventors: Yong Ho BAEK, Joo Hwan JUNG, Young Sik HUR, Jung Chul GONG, Han KIM
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Patent number: 10153235Abstract: The present disclosure relates to an image sensor device including: a fan-out semiconductor package including a first semiconductor chip having an active surface on which a connection pad is disposed, a first connection member disposed on the active surface and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, and a sealing material disposed on the first connection member and sealing at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the first connection member and electrically connected to the first connection member; and a third semiconductor chip disposed on the second semiconductor chip and electrically connected to the second semiconductor chip, in which at least one of the second semiconductor chip or the third semiconductor chip may be an image sensor. The present disclosure also relates to an image sensor module including the image sensor device.Type: GrantFiled: August 21, 2017Date of Patent: December 11, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Kwon Jung, Bang Chul Ko, Chul Choi, Jung Hyun Cho, Joo Hwan Jung, Yong Ho Baek, Seung Eun Lee
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Publication number: 20180286790Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.Type: ApplicationFiled: June 6, 2018Publication date: October 4, 2018Inventors: Jung Hyun CHO, Yong Ho BAEK, Jun Oh HWANG, Joo Hwan JUNG, Moon Hee YI
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Patent number: 10026678Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.Type: GrantFiled: July 12, 2017Date of Patent: July 17, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jung Hyun Cho, Yong Ho Baek, Jun Oh Hwang, Joo Hwan Jung, Moon Hee Yi
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Publication number: 20180182691Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole and having a passive component disposed in the first connection member; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed therein and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the passive component is electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the second connection member.Type: ApplicationFiled: July 12, 2017Publication date: June 28, 2018Inventors: Jung Hyun CHO, Yong Ho BAEK, Jun Oh HWANG, Joo Hwan JUNG, Moon Hee YI
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Publication number: 20180130750Abstract: The present disclosure relates to an image sensor device including: a fan-out semiconductor package including a first semiconductor chip having an active surface on which a connection pad is disposed, a first connection member disposed on the active surface and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, and a sealing material disposed on the first connection member and sealing at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the first connection member and electrically connected to the first connection member; and a third semiconductor chip disposed on the second semiconductor chip and electrically connected to the second semiconductor chip, in which at least one of the second semiconductor chip or the third semiconductor chip may be an image sensor. The present disclosure also relates to an image sensor module including the image sensor device.Type: ApplicationFiled: August 21, 2017Publication date: May 10, 2018Inventors: Dae Kwon JUNG, Bang Chul KO, Chul CHOI, Jung Hyun CHO, Joo Hwan JUNG, Yong Ho BAEK, Seung Eun LEE
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Publication number: 20180068952Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.Type: ApplicationFiled: October 31, 2017Publication date: March 8, 2018Inventors: Moon Hee YI, Joo Hwan JUNG, Yul Kyo CHUNG
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Patent number: 9875970Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.Type: GrantFiled: January 24, 2017Date of Patent: January 23, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Moon Hee Yi, Joo Hwan Jung, Yul Kyo Chung
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Publication number: 20170309571Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.Type: ApplicationFiled: January 24, 2017Publication date: October 26, 2017Inventors: Moon Hee YI, Joo Hwan JUNG, Yul Kyo CHUNG
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Patent number: 9420709Abstract: Disclosed herein are a coreless board for a semiconductor package and a method of manufacturing the same. The coreless board for the semiconductor package includes: a support; a build-up layer formed on the support; an external connection terminal formed on the build-up layer; and a solder resist layer formed on the build-up layer so as to expose the external connection terminal.Type: GrantFiled: March 6, 2014Date of Patent: August 16, 2016Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Young Kwan Lee, Myung Sam Kang, Joo Hwan Jung, Ju Hee Park, Seung Yeop Kook
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Publication number: 20150156891Abstract: Disclosed herein are a printed circuit board and a manufacturing method thereof capable of improving poor inter-layer conduction by increasing inter-layer insulating property and rigidity. The manufacturing method of a printed circuit board includes: laminating a copper foil layer on upper and lower surfaces of an insulating layer; coating an insulating material on a surface of the copper foil layer; forming a circuit layer by etching the copper foil layer; laminating an insulator on the copper foil layer so as to enclose the insulating material and the circuit layer; forming a via in the insulator so as to be communicated with the circuit layer; and forming a circuit pattern on the insulator.Type: ApplicationFiled: March 13, 2014Publication date: June 4, 2015Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Ki Jung SUNG, Myung Sam KANG, Joo Hwan JUNG, Seung Yeop KOOK, Young Kwan LEE
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Publication number: 20150156865Abstract: Disclosed herein are a coreless board for a semiconductor package and a method of manufacturing the same. The coreless board for the semiconductor package includes: a support; a build-up layer formed on the support; an external connection terminal formed on the build-up layer; and a solder resist layer formed on the build-up layer so as to expose the external connection terminal.Type: ApplicationFiled: March 6, 2014Publication date: June 4, 2015Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Young Kwan LEE, Myung Sam KANG, Joo Hwan JUNG, Ju Hee PARK, Seung Yeop KOOK