Abstract: A display that includes a display panel and a window laminated with the display panel is presented. The display panel may include: a main panel region including a first side extending in a first direction and a second side extending in a second direction crossing the first direction; a first sub-panel region that is in contact with the first side and is bent; and a second sub-panel region that is in contact with the second side and is bent. A panel corner part of the main panel region adjacent to the first sub-panel region and the second sub-panel region is rounded.

Abstract: A system and method for machine learning. The system includes a GPU with a GPU memory, and a key value storage device connected to the GPU memory. The method includes, writing, by the GPU, a key value request to a key value request queue in a input-output region of the GPU memory, the key value request including a key. The method further includes reading, by the key value storage device, the key value request from the key value request queue, and writing, by the key value storage device, in response to the key value request, a value to the input-output region of the GPU memory, the value corresponding to the key of the key value request.

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

Abstract: An accelerator is disclosed. The accelerator may include a memory that may store a dictionary table. An address generator may be configured to generate an address in the dictionary table based on an encoded value, which may have an encoded width. An output filter may be configured to filter a decoded value from the dictionary table based on the encoded value, the encoded width, and a decoded width of the decoded data. The accelerator may be configured to support at least two different encoded widths.

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

Abstract: Computing resources are optimally allocated for a multipath neural network using a multipath neural network analyzer that includes an interface and a processing device. The interface receives a multipath neural network that includes two or more paths. A first path includes one or more layers. A first layer of the first path corresponds to a first kernel that runs on a compute unit that includes two or more cores. The processing device allocates to the first kernel a minimum number of cores of the compute unit and a maximum number of cores of the compute unit. The minimum number of cores of the compute unit is allocated based on the first kernel being run concurrently with at least one other kernel on the compute unit and the maximum number of cores of the compute unit is allocated based on the first kernel being run alone on the compute unit.

Abstract: Computing resources may be optimally allocated for a multipath neural network using a multipath neural network analyzer that includes an interface and a processing device. The interface receives a multipath neural network. The processing device generates the multipath neural network to include one or more layers of a critical path through the multipath neural network that are allocated a first allocation of computing resources that are available to execute the multipath neural network. The critical path limits throughput of the multipath neural network. The first allocation of computing resources reduces an execution time of the multipath neural network to be less than a baseline execution time of a second allocation of computing resources for the multipath neural network. The first allocation of computing resources for a first layer of the critical path is different than the second allocation of computing resources for the first layer of the critical path.

Abstract: A method of processing data in a system having a host and a storage node may include performing a shuffle operation on data stored at the storage node, wherein the shuffle operation may include performing a shuffle write operation, and performing a shuffle read operation, wherein at least a portion of the shuffle operation is performed by an accelerator at the storage node. A method for partitioning data may include sampling, at a device, data from one or more partitions based on a number of samples, transferring the sampled data from the device to a host, determining, at the host, one or more splitters based on the sampled data, communicating the one or more splitters from the host to the device, and partitioning, at the device, data for the one or more partitions based on the one or more splitters.

Abstract: A system and method for memory management. In one embodiment, the method includes generating a dependency structure comprising one or more task identifiers and one or more data object identifiers. The dependency structure includes a list of one or more dependencies for a first data object identifier of the one or more data object identifiers, a first dependency of the list identifying a first task for which a data object identified by the first data object identifier is an input. The method further includes counting the number of dependencies for the first data object identifier, decrementing the count by one when the first task completes execution, and, when the count reaches zero, deallocating the first data object.

Abstract: A system and method for machine learning, with a processing circuit executing an operating system, the processing circuit being connected to a first memory and to a second memory. In some embodiments, the method includes: requesting, by a user level process, from the operating system, a first memory allocation from the first memory, the first memory allocation including a plurality of first segments, a first segment of the plurality of first segments having a size sufficient to store a data object of a first kind; determining, by the user level process, that a result of a first calculation will be a data object of the first kind; and in response to determining that the result of the first calculation will be a data object of the first kind: determining, by the user level process, that none of the first segments are unused.

Abstract: An accelerator is disclosed. The accelerator may include a memory that may store a dictionary table. An address generator may be configured to generate an address in the dictionary table based on an encoded value, which may have an encoded width. An output filter may be configured to filter a decoded value from the dictionary table based on the encoded value, the encoded width, and a decoded width of the decoded data. The accelerator may be configured to support at least two different encoded widths.

Abstract: A method of processing data may include receiving a stream of first keys associated with first data, receiving a stream of second keys associated with second data, comparing, in parallel, a batch of the first keys and a batch of the second keys, collecting one or more results from the comparing, and gathering one or more results from the collecting. The collecting may include reducing an index matrix and a mask matrix. Gathering one or more results may include storing, in a leftover vector, at least a portion of the one or more results from the collecting. Gathering one or more results further may include combining at least a portion of the leftover vector from a first cycle with at least a portion of the one or more results from the collecting from a second cycle.

Abstract: A method of shuffling data may include shuffling a first batch of data using a first memory on a first level of a memory hierarchy to generate a first batch of shuffled data, shuffling a second batch of data using the first memory to generate a second batch of shuffled data, and storing the first batch of shuffled data and the second batch of shuffled data in a second memory on a second level of the memory hierarchy. The method may further include merging the first batch of shuffled data and the second batch of shuffled data. A data shuffling device may include a buffer memory configured to stream one or more records to a partitioning circuit and transfer, by random access, one or more records to a grouping circuit.

Abstract: A system and method for machine learning. The system includes a GPU with a GPU memory, and a key value storage device connected to the GPU memory. The method includes, writing, by the GPU, a key value request to a key value request queue in a input-output region of the GPU memory, the key value request including a key. The method further includes reading, by the key value storage device, the key value request from the key value request queue, and writing, by the key value storage device, in response to the key value request, a value to the input-output region of the GPU memory, the value corresponding to the key of the key value request.

Abstract: A method of processing data in a system having a host and a storage node may include performing a shuffle operation on data stored at the storage node, wherein the shuffle operation may include performing a shuffle write operation, and performing a shuffle read operation, wherein at least a portion of the shuffle operation is performed by an accelerator at the storage node. A method for partitioning data may include sampling, at a device, data from one or more partitions based on a number of samples, transferring the sampled data from the device to a host, determining, at the host, one or more splitters based on the sampled data, communicating the one or more splitters from the host to the device, and partitioning, at the device, data for the one or more partitions based on the one or more splitters.

Abstract: A storage system includes: a storage device to store an array of data elements associated with a sort operation; a storage interface to facilitate communications between the storage device and a host computer; and a reconfigurable processing device communicably connected to the storage device, the reconfigurable processing device including: memory to store input data read from the storage device, the input data corresponding to the array of data elements stored in the storage device; and a kernel including one or more compute components to execute the sort operation on the input data stored in the memory according to a SORT command received from the host computer. The reconfigurable processing device is to dynamically instantiate the one or more compute components to accelerate the sort operation.

Abstract: A system and method for machine learning. The system includes a GPU with a GPU memory, and a key value storage device connected to the GPU memory. The method includes, writing, by the GPU, a key value request to a key value request queue in a input-output region of the GPU memory, the key value request including a key. The method further includes reading, by the key value storage device, the key value request from the key value request queue, and writing, by the key value storage device, in response to the key value request, a value to the input-output region of the GPU memory, the value corresponding to the key of the key value request.

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

Abstract: A storage system includes: a storage device to store an array of data elements associated with a sort operation; a storage interface to facilitate communications between the storage device and a host computer; and a reconfigurable processing device communicably connected to the storage device, the reconfigurable processing device including: memory to store input data read from the storage device, the input data corresponding to the array of data elements stored in the storage device; and a kernel including one or more compute components to execute the sort operation on the input data stored in the memory according to a SORT command received from the host computer. The reconfigurable processing device is to dynamically instantiate the one or more compute components to accelerate the sort operation.