Abstract: A semiconductor memory device including a shift redundancy circuit with two buffer chains, two fuses connected to the shift redundancy circuit, a plurality of fuse cut-out detecting circuits for detecting cut-out status of the fuses, and two spare cell control circuits for controlling two spare memory cell rows, wherein word line control signals for controlling corresponding word lines connected to memory cells in a memory cell array are shifted upward and downward to control respective next word lines, thereby replacing two defective memory cell rows with the two spare memory cell rows.

Abstract: A method and apparatus inserts virtual advertisements or other virtual contents into a sequence of frames of a video presentation by performing real-time content-based video frame processing to identify suitable locations in the video for implantation. Such locations correspond to both the temporal segments within the video presentation and the regions within an image frame that are commonly considered to be of lesser relevance to the viewers of the video presentation. This invention presents a method and apparatus that allows a non-intrusive means to incorporate additional virtual content into a video presentation, facilitating an additional channel of communications to enhance greater video interactivity.

Abstract: A remote-plasma ALD apparatus includes a reaction chamber, an exhaust line for exhausting gas from the reaction chamber, a first reactive gas supply unit for selectively supplying a first reactive gas to the reactant chamber or the exhaust line, a first reactive gas transfer line for connecting the first reactive gas supply unit and the reactant chamber, a first bypass line for connecting the first reactive gas supply line and the exhaust line, a radical supply unit for generating radicals and selectively supplying the radicals to the reactant chamber or the exhaust line, a radical transfer line for connecting the radical supply unit and the reactant chamber, a second bypass line for connecting the radical supply unit and the exhaust line, and a main purge gas supply unit for supplying a main purge gas to the first reactant transfer line and/or the radical transfer line.

Abstract: A transflective type LCD device and a method for manufacturing the same is disclosed, in which an aperture ratio of a reflective part is improved, and manufacturing process is simplified by decreasing the number of masks for forming contact holes. The transflective type LCD device includes a plurality of gate and data lines crossing each other, defining a plurality of pixel regions; a thin film transistor at a crossing point of the gate and data lines; a lower storage electrode formed by one portion of a preceding gate line, and an upper storage electrode above the lower storage electrode having a gate insulating layer in between; a transmitting electrode in contact the upper storage electrode; and a reflective electrode in contact with the transmitting electrode in the reflective part of the pixel region wherein the transmitting electrode is in between the reflective electrode and the substrate.

Abstract: The present invention relates to bit cell arrays of read-only-memories, and more specifically, to a bit cell array capable of preventing a coupling effect between adjacent bit lines. In addition, the bit cell array according to the present invention does not require an additional device in order to prevent the coupling effect. In accordance with the present invention, the bit cell array comprising: a plurality of bit lines arranged in a row in a first direction; a plurality of ground lines in a row in a second direction vertical to the first direction; a plurality of word lines arranged with a zigzag line with respect to the second direction; and a plurality of ROM bit cells partially formed at a cross-section point of the bit lines and the word lines. In the meanwhile, the ROM bit cells are arranged with a zigzag line with respect to adjacent bit lines. Additionally, the ROM bit cells comprise a drain terminal, a gate terminal and a source terminal.

Abstract: Provided is a thin film deposition reactor, including a reactor block having a deposition space, a wafer block, a top lid for covering and sealing the reactor block, a showerhead for spraying a reaction gas on the wafer block, and an exhaust line through which gases are exhausted from the reactor block. A lower pumping baffle and an upper pumping baffle are stacked on a bottom of the reactor block between an outer circumference of the wafer block and an inner circumference of the reactor block. A lower pumping region is formed between the lower pumping baffle and an inner sidewall of the reactor block. An upper pumping region is formed between the upper pumping baffle and the inner sidewall of the reactor block. The deposition space is connected to the upper pumping region by a plurality of upper pumping holes formed in the upper pumping baffle, and the upper pumping region is connected to the lower pumping region by a plurality of lower pumping holes formed in the lower pumping baffle.

Abstract: A liquid crystal display device includes a first substrate divided into a first active region and a first dummy region surrounding the first active region, a plurality of data lines and gate lines arranged on the first substrate along lengthwise and widthwise directions to define a plurality of pixel regions, a common voltage line formed within the first dummy region, a plurality of active pixels formed within the first active region each having a pixel electrode, a plurality of test pixels formed within the first dummy region each having a pixel electrode, a second substrate divided into a second active region and a second dummy region surrounding the second active region and bonded to the first substrate, a first black matrix formed within the second dummy region having openings corresponding to the test pixels, a second black matrix formed within the second dummy region to overlap the pixel electrodes of the test pixels by a plurality of different widths, and a common electrode formed on the second substra

Abstract: A method of cleaning a deposition chamber includes applying an RF power to a first region of a deposition chamber where a metal oxide layer is attached. The metal oxide layer in the first region is thicker than the metal oxide layer existing at a second region of the deposition chamber. The RF power increases a plasma sheath potential in the first region to a value that is greater than that of a plasma sheath potential in the second region. An etching gas is introduced into the deposition chamber to remove the metal oxide layer. The metal oxide layer attached to the deposition chamber may be rapidly removed by the in-situ process without opening of the deposition chamber.

Abstract: Provided is a thin film deposition reactor. The reactor includes a reactor block including a wafer block on which a wafer is mounted; a top lid for covering and sealing the reactor block; a showerhead disposed under the top lid and connected to an RF power supply unit, the showerhead having first nozzles and second nozzles that are not combined with each other; a showerhead isolation assembly having a plurality of gas curtain holes for forming a gas curtain around the wafer block, the showerhead isolation assembly for isolating the top lid from the showerhead; a top lid isolation flow line disposed on the top lid, the top lid isolation flow line having a first flow line and a second flow line that are connected to the first nozzles and the second nozzles, respectively, and are each bent at a right angle at least once.

Abstract: A reactor for thin film deposition and a thin film deposition method using the reactor are provided. The reactor includes: a reactor block which receives a wafer transferred through a wafer transfer slit; a wafer block which is installed in the reactor block to receive the wafer thereon; a top plate disposed to cover the reactor block; a shower head which is mounted on the bottom of the top plate and diffuses gas toward the wafer; and an exhaust unit which exhausts the gas from the reactor block. A first supply pipeline which supplies a first reactant gas and/or an inert gas to the wafer; a second supply pipeline which supplies a second reactant gas and/or an inert gas to the wafer; and a plasma generator which generates plasma between the wafer block and shower head are included.

Abstract: Provided is a thin film deposition reactor, including a reactor block having a deposition space, a wafer block, a top lid for covering and sealing the reactor block, a showerhead for spraying a reaction gas on the wafer block, and an exhaust line through which gases are exhausted from the reactor block. A lower pumping baffle and an upper pumping baffle are stacked on a bottom of the reactor block between an outer circumference of the wafer block and an inner circumference of the reactor block. A lower pumping region is formed between the lower pumping baffle and an inner sidewall of the reactor block. An upper pumping region is formed between the upper pumping baffle and the inner sidewall of the reactor block. The deposition space is connected to the upper pumping region by a plurality of upper pumping holes formed in the upper pumping baffle, and the upper pumping region is connected to the lower pumping region by a plurality of lower pumping holes formed in the lower pumping baffle.

Abstract: Provided is a method of depositing an ALD thin film. The method includes (S1) loading a wafer on a wafer block; (S2) depositing the ALD thin film on the wafer; (S3) unloading the wafer, on which the ALD thin film is deposited, from the wafer block; (S4-1) loading a dummy wafer on the wafer block; (S4-2) stabilizing the flow rates and the pressures of gases in the reactor by spraying only an inert gas or a mixture of the inert gas and a cleaning gas in the reactor; (S4-3) supplying RF power to the showerhead so as to activate the cleaning gas and mostly removing a thin film deposited on a surface of the showerhead by using the activated cleaning gas; (S4-4) unloading the dummy wafer from the wafer block; (S4-5) repeating steps 4-1 through 4-4 at least once using new dummy wafers; and (S5) purging the inside of the reactor.

Abstract: Provided is a reaction chamber for depositing a thin film. The reaction chamber includes a reactor block; a wafer block located inside the reactor block; a top plate that covers the reactor block to maintain a predetermined pressure; a feeding unit which supplies reactive gases to the reactor block; a shower head, which is installed in the top plate and includes a plurality of first spray holes for spraying the first reactive gas on a wafer and a plurality of second spray holes for spraying the second reactive gas; and an exhaust unit which expels gases from the reactor block. The feeding unit includes a feeding block; a distributing block; two or more first gas transfer pipes; and a second gas transfer pipe. The shower head includes an upper diffusion block, an intermediate diffusion block, and a lower diffusion block.

Abstract: Provided is a method of depositing a thin film using a hafnium compound. In this method, the depositing (S200) of a thin film includes (S20) depositing a primary thin film and (S21) depositing a secondary thin film. Step (S200) is performed by repeating steps (S20) and (S21) once or more. Step (S20) includes (S20-1) feeding a first reactive gas, (S20-2) purging the first reactive gas, (S20-3) feeding a third reactive gas, and (S20-4) purging the third reactive gas. Step (S21) includes (S21-1) feeding a second reactive gas, (S21-2) purging the second reactive gas, (S21-3) feeding the third reactive gas, and (S21-4) purging the third reactive gas. Step (S20) is performed by repeating steps (S20-1), (S20-2), (S20-3), and (S20-4) N times, and step (S21) is performed by repeating steps (S21-1), (S21-2), (S21-3), and (S21-4) M times.

Abstract: Provided is a method of depositing a thin film on a wafer using an aluminum compound. The method includes (S1) mounting the wafer on the wafer block; and (S2) depositing an Al2O3 thin film. Step (S2) includes (S2-1) feeding ozone by spraying ozone through the first spray holes and spraying an inert gas through the second spray holes; (S2-2) purging the ozone by stopping the spraying of the ozone, spraying the inert gas through the first spray holes, and spraying the same inert gas as in step (S2-1) through the second spray holes; (S2-3) feeding TMA by spraying the TMA, which is transferred by a carried gas, through the second spray holes and spraying the inert gas through the first spray holes; and (S2-4) purging the TMA by stopping the spraying of the TMA, spraying the same carrier gas as in step (S2-3) through the second spray holes, and spraying the same inert gas as in step (S2-3) through the first spray holes.

Abstract: A semiconductor memory device including a shift redundancy circuit with two buffer chains, two fuses connected to the shift redundancy circuit, a plurality of fuse cut-out detecting circuits for detecting cut-out status of the fuses, and two spare cell control circuits for controlling two spare memory cell rows, wherein word line control signals for controlling corresponding word lines connected to memory cells in a memory cell array are shifted upward and downward to control respective next word lines, thereby replacing two defective memory cell rows with the two spare memory cell rows.

Abstract: A FIFO memory device includes a write address generating circuit generating a write address in response to a write clock signal and a read address generating circuit generating a read address in response to a read clock signal. A memory cell array includes a plurality of memory cells arranged between a plurality of write and read word lines and a plurality of write and read bit lines, the memory cell array storing write data in response to the write address and outputting read data in response to the read address. A flag signal generating circuit compares a next write address with a current read address to generate a full flag signal in response to the write clock signal when the next write address and the current read address are equal, and compares a current write address with a next read address to generate an empty flag signal in response to the read clock signal when the current write address and the next read address are equal.

Abstract: A FIFO memory device includes a write address generating means generating a write address in response to a write clock signal and a read address generating means generating a read address in response to a read clock signal. A memory cell array includes a plurality of memory cells arranged between a plurality of write and read word lines and a plurality of write and read bit lines, the memory cell array storing write data in response to the write address and outputting read data in response to the read address. A flag signal generating means compares a next write address with a current read address to generate a full flag signal in response to the write clock signal when the next write address and the current read address are equal, and compares a current write address with a next read address to generate an empty flag signal in response to the read clock signal when the current write address and the next read address are equal.

Abstract: A thin film transistor and method includes a substrate and a first semiconductor layer formed on the substrate. A first insulating layer is formed on the first semiconductor layer, and a doped semiconductor layer is formed on an upper portion of the first semiconductor layer at first and second sides of the first insulating layer. A second insulating layer is formed on the first insulating layer and the doped semiconductor layer, the second insulating layer having contact holes. A gate electrode is formed on a portion of the second insulating layer, and source and drain electrodes are formed on portions of the second insulating layer, the source and drain electrodes contacting the doped semiconductor layer through the contact holes, respectively.