Abstract: The present invention discloses an internal power voltage generator of a semiconductor device which can actively control standby tape pumps and active tape pumps according to a magnitude of an internal power voltage.

Abstract: A multi-bank semiconductor memory device includes a multi-bank memory; a voltage generator having one standby driving circuit and a plurality of active driving circuits and supplying a power source voltage required for a semiconductor device; and, an up/down counter for counting a low access signal and a low precharge signal and outputting a multi-bit driving enable signal for driving the plurality of active driving circuits differentially in performing an interleaving operation. When a plurality of banks are accessed, the number of banks being currently accessed is counted by using the low access signal and the low precharge signal. The number of the voltage driving circuits is increased and decreased according to the count value.

Abstract: An apparatus for selecting banks in a semiconductor memory device provides a half-chip by adjusting all bits including the most significant bit (MSB) of bank addresses to select normal banks even if degraded banks are included in both upper and lower bank blocks. In a memory including an upper bank block and a lower bank block which are constructed with a plurality of banks selectable by a plurality of bank addresses, an apparatus for selecting the banks includes a plurality of bank address control parts each corresponding to one address bit of the bank addresses, each of the bank address control part applying a fixed logic value to the upper and lower bank blocks according to a selective cutting of at least one of the fuses, and each of the bank address control parts applying either a corresponding bank address bit input thereto or a bank address bit just below the corresponding bank address bit to the upper and lower bank blocks.

Abstract: An apparatus for varying a data input/output path in a memory device, includes DBSAs amplifying a signal loaded on a data bus, fuse circuits producing output signals of specific levels respectively in accordance with whether or not fuses are cut, input multiplexers each of which selects either an external signal inputted through a corresponding pad or another external signal inputted through a pad next to the corresponding pad in accordance with the output signals of the fuse circuits, and applies the selected signal to a write driver, and data input/output parts including output multiplexers, each of the output multiplexers selecting a signal outputted from either a corresponding one of the DBSAs or one next to the corresponding DBSA in accordance with the output signals of the fuse circuits, and outputting the selected signal through a corresponding pad.

Abstract: A power module package is provided. The power module package includes a power circuit element, a control circuit element, a lead frame, a heat sink, and an epoxy molding compound (EMC). The control circuit element is connected to the power circuit and controls chips in the power circuit. The lead frame has external connecting means formed at the edges thereof, and a down set part, namely, formed between the external connecting means. The lead frame has a first surface to which the power circuit and the control circuit are attached, and a second surface used as a heat dissipating path, in particular, the power circuit is attached to the down set part. The heat sink which is closely attached to the down set part of the second surface of the lead frame by an adhesive. The EMC surrounds the power circuit, the control circuit, the lead frame and the heat sink, and exposes the external connecting means of the lead frame and a side of the heat sink.

Abstract: A multi-bank semiconductor memory device includes a multi-bank memory; a voltage generator having one standby driving circuit and a plurality of active driving circuits and supplying a power source voltage required for a semiconductor device; and, an up/down counter for counting a low access signal and a low precharge signal and outputting a multi-bit driving enable signal for driving the plurality of active driving circuits differentially in performing an interleaving operation. When a plurality of banks are accessed, the number of banks being currently accessed is counted by using the low access signal and the low precharge signal. The number of the voltage driving circuits is increased and decreased according to the count value.

Abstract: An apparatus for selecting banks in a semiconductor memory device provides a half-chip by adjusting all bits including the most significant bit (MSB) of bank addresses to select normal banks even if degraded banks are included in both upper and lower bank blocks. In a memory including an upper bank block and a lower bank block which are constructed with a plurality of banks selectable by a plurality of bank addresses, an apparatus for selecting the banks includes a plurality of bank address control parts each corresponding to one address bit of the bank addresses, each of the bank address control part applying a fixed logic value to the upper and lower bank blocks according to a selective cutting of at least one of the fuses, and each of the bank address control parts applying either a corresponding bank address bit input thereto or a bank address bit just below the corresponding bank address bit to the upper and lower bank blocks.

Abstract: An apparatus for varying a data input/output path in a memory device, includes DBSAs amplifying a signal loaded on a data bus, fuse circuits producing output signals of specific levels respectively in accordance with whether or not fuses are cut, input multiplexers each of which selects either an external signal inputted through a corresponding pad or another external signal inputted through a pad next to the corresponding pad in accordance with the output signals of the fuse circuits, and applies the selected signal to a write driver, and data input/output parts including output multiplexers, each of the output multiplexers selecting a signal outputted from either a corresponding one of the DBSAs or one next to the corresponding DBSA in accordance with the output signals of the fuse circuits, and outputting the selected signal through a corresponding pad.

Abstract: The present invention discloses an internal power voltage generator of a semiconductor device which can actively control standby tape pumps and active tape pumps according to a magnitude of an internal power voltage.

Abstract: A fuse repair circuit for a semiconductor memory device includes a cell array provided with a row redundancy and a column redundancy and a fuse block for driving the row redundancy during a RAS cycle and driving the column redundancy during a CAS cycle, wherein the fuse block consists of an address input unit for selectively outputting a row address or a column address in accordance with switching signals, a plurality of fuse units, wherein redundancy information of a defective cell is programmed, for comparing an inputted address with the programmed redundancy information, and a redundancy driving unit for outputting a matching signal for driving the row redundancy or the column redundancy when the inputted address and the programmed redundancy information are identical.