Abstract: A buried bit line cell and a manufacturing method thereof increases the integration density of a semiconductor device such as a DRAM.

Abstract: A method of projection exposure utilizing a mask including a step of exposing an object by utilizing a transparent mask substrate of which the upper surface is slanted at a predetermined angle from a direction perpendicular to the light path and an opaque film pattern is formed at regular intervals on a lower surface of the mask substrate so that the phase difference between adjacent mask patterns occurs due to the slanted mask substrate, thereby reducing the minimum pitch available for pattern formation without a shorter-wavelength light source and without increasing NA by reducing the frequency difference .delta.v to the pitch d of the mask in a given wavelength of a light source and NA.

Abstract: A method for fabricating an integrated circuit device includes the steps of forming an insulating layer on a substrate and forming a plurality of parallel conductive lines on the insulating layer. An etch barrier is formed on each of the parallel conductive lines, and contact holes are formed between the etch barriers. The contact holes expose portions of the substrate without exposing the plurality of parallel conductive lines. In particular, the contact holes can be formed by forming a patterned mask layer on the insulating layer and etch barriers, and etching exposed portions of the insulating layer. The patterned mask layer selectively exposes a plurality of parallel strips orthogonal to the plurality of parallel conductive lines. Related structures are also discussed.

Abstract: A semiconductor memory device provided with capacitors formed above and below a cell transistor includes first and second transistors formed in a first level, a first storage electrode connected to the first transistor and formed below the first level, and a second storage electrode connected to the second transistor and formed above the first level. The first and second storage electrodes are connected to each source via a spacer formed on the sidewalls of each source, and undercuts are formed between the storage electrode and the transistor, to thereby obtain double or more cell capacitance, a stable cell transistor characteristic and reduced short-channel effects.

Abstract: A semiconductor memory device provided with capacitors formed above and below a cell transistor includes first and second transistors formed in a first level, a first storage electrode connected to the first transistor and formed below the first level, and a second storage electrode connected to the second transistor and formed above the first level. The first and second storage electrodes are connected to each source via a spacer formed on the sidewalls of each source, and undercuts are formed between the storage electrode and the transistor, to thereby obtain double or more cell capacitance, stable cell transistor characteristic and reduced short-channel effects.

Abstract: A capacitor of a semiconductor device has a plate electrode which process margin and a method of manufacturing same are disclosed. The plate electrode has a planarized surface and borders a source region. A recessed field oxide layer defining an active region is formed on a semiconductor substrate. Then, an insulating pattern for self-aligning an electrode is formed on the active region. The insulating pattern has a step with respect to the field oxide layer. Thereafter, a trench is formed in the semiconductor substrate by partially removing the field oxide layer, the insulating pattern and a surface portion of the semiconductor substrate. A conductive material is deposited on the semiconductor substrate having the trench and the insulating pattern to form a conductive layer filling the trench. Then, the conductive layer is polished until the insulating pattern is exposed, to thereby obtain an electrode having a planarized surface.