Abstract: The present invention provides: a method for manufacturing an insulated conductive pattern, wherein a conductive film and an insulation layer pattern are formed on a substrate, and the insulation layer pattern is reformed to cover a conductive pattern after formation of the conductive pattern by etching the conductive film using the insulation layer pattern as a mask; and a laminate manufactured thereby. According to the present invention, the number of processes is sharply reduced in comparison with the existing processes, and economic efficiency can be greatly improved.

Abstract: A lumbar support device of a seat for a vehicle surrounds and supports the lumbar region of a passenger. In the lumbar support device, a mounting bracket is fastened to a seat back frame. A support panel is coupled to the mounting bracket through link units so as to be movable ahead of the seat back frame. Side support units are coupled to respective opposite ends of the support panel so as to be rotatable. A connection wire is connected between each of the side support units and the corresponding link unit of the support panel such that when the support panel moves forwards, the side support units surround side portions of the lumbar region of the passenger.

Abstract: The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.

Abstract: A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state.

Abstract: Provided are a bacterium-based microrobot for medical treatment, an operation method thereof, and a treatment method using the same. The bacterium-based microrobot can be propelled by the flagellum movement of bacteria, can be directed toward a target lesion by the ability of bacteria to recognize the lesion, can be monitored for how many the microrobot targets the lesion, and can directly or indirectly treat the lesion by the proliferation of bacteria through self-division in the lesion. The bacteria may be genetically manipulated to be resistant to immune responses and produce a material inhibitory of the growth of affected cells.

Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Abstract: An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.

Abstract: A method writes data to a resistance random access memory (RRAM) memory cell through first and second write paths, and includes; applying a positive source voltage to a selected source line, applying a word line drive voltage to a selected word line, and applying a voltage at least twice the level of the positive source voltage to a selected bit line via the first write path when writing data having the first state in the memory cell, and applying a ground voltage to the selected bit line via the second write path when writing data having the second state in the memory cell.

Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Abstract: A semiconductor memory device having an efficient core structure for multi-writing includes a data input/output line, a plurality of memory banks each comprising a plurality of memory cells, a first global bit line and a second global bit line which are shared by the plurality of memory banks, and a first write driver and a second write driver which are connected with the data input/output line and provide a program current to the plurality of memory banks through the first and second global bit lines, respectively. Each memory bank includes a first cell area connected with the first global bit line and a second cell area connected with the second global bit line.

Abstract: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.

Abstract: The present invention provides a nonvolatile memory device that uses a resistance material. The nonvolatile memory device includes: a stacked memory cell array having a plurality of memory cell layers stacked in a vertical direction, the stacked memory cell array having at least one memory cell group and at least one redundancy memory cell group; and a repair control circuit coupled to the stacked memory cell array, the repair control circuit configured to repair a defective one of the at least one memory cell group with a selected one of the at least one redundancy memory cell group. The features that enable repair improve the fabrication yield of the nonvolatile memory device.

Abstract: A non-volatile memory device includes a memory cell array including a memory cell array having word lines, bit lines, and non-volatile memory cells, each non-volatile memory cell having a variable resistive material and an access element connected between the corresponding word line and the corresponding bit line. The variable resistive material has a resistance level that varies according to data to be stored. A selection circuit selects at least one non-volatile memory cell in which data will be written. An adaptive write circuit/method supplies a write bias to the selected non-volatile memory cell through the bit line connected to the selected non-volatile memory cell to write data in the selected non-volatile memory cell and varies (e.g., increases) the write bias until the resistance level of the selected non-volatile memory cell varies.

Abstract: A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided.

Abstract: A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite directions, includes word lines, bit lines, a memory cell array and a plurality of source lines. The memory cell array includes a plurality of memory cells each constructed of an access transistor coupled to a resistive memory device. The memory cells are disposed in a matrix of rows and columns and located at each intersection of a word line and a bit line. Each of the plurality of source lines is disposed between a pair of word lines and in the same direction as the word lines. A positive voltage is applied to a source line in a memory cell write operation.

Abstract: An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.

Abstract: A phase-change random access memory (PRAM) device includes a PRAM cell array including a first sector and a second sector, a first global bit line coupled to a first local bit line of the first sector and a first local bit line of the second sector, and a first plurality of global bit line discharge units coupled to the first global bit line, the first plurality of global bit line discharge units configured to discharge the first global bit line in response to a first global discharge signal.

Abstract: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.

Abstract: A non-volatile memory device is employed in which data values are determined by the polarities at both ends of a cell, The non-volatile memory device includes a first decoder which decodes a plurality of predetermined bit values of a row address into a first address and is disposed in a row direction of a memory cell array; a second decoder which decodes the other bit values of the row address into a second address and is disposed in a column direction of the memory cell array; and a driver which applies bias voltages to a word line which corresponds to the first address or the second address in accordance with the data values. By including first and second decoders and decoding a row address in two steps, a bi-directional RRAM according to the present invention can perform addressing at high speeds while reducing chip size.

Abstract: A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided.