Patents by Inventor Joon-Seok Oh

Joon-Seok Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240199780
    Abstract: The objective of the present invention is to provide a fluorine-based polymer having a low surface energy, a fluorine-based polymer composition comprising same, a fluorine-based polymer membrane comprising same, and a method for manufacturing same. The present invention provides an acrylate-based copolymer, and in particular, the present invention is characterized in that the number of fluorocarbons in the repeating unit is limited to 3 to 5, such that the surface energy of the polymer and the polymer membrane produced therefrom is significantly lowered. In addition, when the polymer of the present invention is coated on glass, etc., the polymer has the effect of remarkably improving light transmittance, and has excellent mechanical strength.
    Type: Application
    Filed: February 7, 2022
    Publication date: June 20, 2024
    Inventors: Eun-Ho SOHN, Won Wook SO, In Joon PARK, Bong Jun CHANG, Ju Hyeon KIM, Ji Hoon BAIK, Myung Seok OH, Jong Min KIM, Sang Goo LEE, Myoung Sook LEE, Hyeon Jun HEO, Shin Hong YOOK
  • Patent number: 11986523
    Abstract: Disclosed is a stable liquid formulation, comprising an antibody or antigen-binding portion thereof, an acetate buffer, glycine, and a surfactant, wherein the stable liquid formulation does not comprise at least one of sugar, a sugar alcohol and a metal salt, and the stable liquid formulation is still stable even upon high antibody content, and is superior in osmolality and viscosity, and subcutaneous administration thereof is possible.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: May 21, 2024
    Assignee: CELLTRION INC.
    Inventors: Joon Won Lee, Yeon Kyeong Shin, Hye Young Kang, Kwang Woo Kim, So Young Kim, Su Jung Kim, Jun Seok Oh, Won Yong Han
  • Patent number: 11970558
    Abstract: A method of recovering a solvent including: supplying polymerization reactants including one or more monomers and a solvent to a reactor to obtain a polymer solution; supplying a stream including the polymer solution to a separator to separate an upper discharge stream including the solvent, wherein the solvent is in a gaseous phase, and a lower discharge stream including the polymer solution; heating a divergence stream including a part of the lower discharge stream from the separator by a heating device and refluxing the divergence stream to the separator; supplying a residue stream including a remainder of the lower discharge stream from the separator to a steam stripping process unit; and adjusting a vapor mass fraction of the divergence stream which is refluxed to the separator with a pressure adjustment valve after being heated by the heating device.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 30, 2024
    Assignee: LG CHEM, LTD.
    Inventors: Suk Yung Oh, Jun Seok Ko, Kwan Sik Kim, Joon Ho Shin, Byeong Gil Lyu, Se Kyung Lee
  • Patent number: 11951207
    Abstract: The present invention provides a stable liquid pharmaceutical formulation containing: an antibody or its antigen-binding fragment; a surfactant; a sugar or its derivative; and a buffer. The stable liquid pharmaceutical formulation according to the present invention has low viscosity while containing a high content of the antibody, has excellent long-term storage stability based on excellent stability under accelerated conditions and severe conditions, and may be administered subcutaneously.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: April 9, 2024
    Assignee: Celltrion Inc.
    Inventors: Joon Won Lee, Won Yong Han, Su Jung Kim, Jun Seok Oh, So Young Kim, Su Hyeon Hong, Yeon Kyeong Shin
  • Publication number: 20240047357
    Abstract: An interconnection structure includes a first dielectric layer, a second dielectric layer, first wiring patterns, and a first conductive pattern. The first wiring patterns respectively include a first penetration part that extends into a surface of the first dielectric layer, a first intervention part on the first penetration part and in the second dielectric layer, and a first connection part on the first intervention part and in the second dielectric layer. A top surface of the first intervention part is at a same level as a top surface of the first conductive pattern relative to the surface of the first dielectric layer. An angle between a sidewall of the first connection part and the top surface of the first intervention part is greater than that between a sidewall of the first penetration part and a bottom surface of the first dielectric layer.
    Type: Application
    Filed: April 26, 2023
    Publication date: February 8, 2024
    Inventors: Yoonyoung Jeon, Youngmin Kim, Joon Seok Oh, Changbo Lee
  • Publication number: 20230387059
    Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 30, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Changbo LEE, KWANHOO SON, JOON SEOK OH
  • Publication number: 20230301180
    Abstract: Embodiments of the present invention relate to: an organic material for an organic electric element, which can improve the driving voltage, luminous efficiency, and service life characteristics of the organic electric element; a method for producing the organic material for an organic electric element; and an organic electric element using same.
    Type: Application
    Filed: July 5, 2021
    Publication date: September 21, 2023
    Inventors: Dae Ho SONG, Jong Gwang PARK, Bum Sung LEE, Jung Hwan PARK, Soung Yun MUN, Yun Suk LEE, Sun Pil HWANG, Joon Seok OH
  • Patent number: 11710715
    Abstract: A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: July 25, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joo Hyung Lee, Ki Tae Park, Byung Lyul Park, Joon Seok Oh, Jong Ho Yun
  • Patent number: 11682648
    Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: June 20, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changbo Lee, Kwanhoo Son, Joon Seok Oh
  • Publication number: 20210384153
    Abstract: A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.
    Type: Application
    Filed: March 22, 2021
    Publication date: December 9, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Joo Hyung LEE, Ki Tae PARK, Byung Lyul PARK, Joon Seok OH, Jong Ho YUN
  • Patent number: 11106137
    Abstract: New photoresist compositions are provided that are useful for immersion lithography. Preferred photoresist compositions of the invention comprise one or more materials that comprise one or more base reactive groups and (i) one or more polar groups distinct from the base reactive groups, and/or (ii) at least one of the base reactive groups is a non-perfluorinated base reactive group. Particularly preferred photoresists of the invention can exhibit reduced leaching of resist materials into an immersion fluid contacting the resist layer during immersion lithography processing.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: August 31, 2021
    Assignees: Rohm and Haas Electronic Materials LLC, Dow Global Technologies LLC
    Inventors: Deyan Wang, Cong Liu, Mingqi Li, Joon Seok Oh, Cheng-Bai Xu, Doris H. Kang, Clark H. Cummins, Matthias S. Ober
  • Publication number: 20210242158
    Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.
    Type: Application
    Filed: October 14, 2020
    Publication date: August 5, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Changbo LEE, KWANHOO SON, JOON SEOK OH
  • Patent number: 10724115
    Abstract: This invention relates to magnetite-based sintered iron ore wherein a magnetite ore powder, which is not currently utilized owing to its low reducibility index among iron ore materials serving as a main material in iron-making processes, is improved so as to have a high reducibility index, and to a method of manufacturing the same.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 28, 2020
    Assignee: Korea University Research and Business Foundation
    Inventors: Joonho Lee, Joon Seok Oh
  • Patent number: 10559540
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating the first and second semiconductor chips, a second connection member disposed on at least one side of the first and second semiconductor chips and including a redistribution layer electrically connected to the first and second semiconductor chips, and an insulating via in which at least a portion of the first connection member is removed in a thickness direction and is filled with an insulating material.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Bo Lee, Joon Seok Oh, Hyun Chul Jung, Jeong Ho Yeo
  • Publication number: 20190164908
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating the first and second semiconductor chips, a second connection member disposed on at least one side of the first and second semiconductor chips and including a redistribution layer electrically connected to the first and second semiconductor chips, and an insulating via in which at least a portion of the first connection member is removed in a thickness direction and is filled with an insulating material.
    Type: Application
    Filed: June 8, 2018
    Publication date: May 30, 2019
    Inventors: Chang Bo LEE, Joon Seok OH, Hyun Chul JUNG, Jeong Ho YEO
  • Patent number: 10237018
    Abstract: A first communication device calculates a plurality of data error codes for detecting an error in a plurality of data fields by using the plurality of data fields. The first communication device generates a packet comprising the plurality of data fields and the plurality of data error codes, and then transmits the packet which is generated to a second communication device.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: March 19, 2019
    Assignee: LSIS CO., LTD.
    Inventors: Sung Han Lee, Dae Hyun Kwon, Joon Seok Oh
  • Publication number: 20190027419
    Abstract: A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a reinforcing plate disposed on the encapsulant and having a first surface facing the inactive surface of the semiconductor chip and a second surface opposing the first surface; and rigid patterns formed on at least one of the first surface and the second surface of the reinforcing plate.
    Type: Application
    Filed: December 1, 2017
    Publication date: January 24, 2019
    Inventors: Chang Bo LEE, Joon Seok OH, Hyun Chul JUNG, Jeong Ho YEO
  • Patent number: 10142058
    Abstract: A method for a first communication device transmitting data to a second communication device, according to one embodiment of the present invention, comprises the steps of: the first communication device generating a safety unique identifier by using a unique identifier of the first communication device and a unique identifier of the second communication device, in order to confirm the validity of connection between the first communication device and the second communication device; the first communication device calculating a data error detection code for detecting an error by using the safety unique identifier and the data; the first communication device generating a packet comprising the data and the data error detection code; and the first communication device transmitting the packet to the second communication device.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: November 27, 2018
    Assignee: LSIS CO., LTD.
    Inventors: Sung Han Lee, Dae Hyun Kwon, Joon Seok Oh
  • Patent number: 10044469
    Abstract: A first communication device calculates a data error detection code for detecting an error in data by using the data and a virtual sequence number, and generates a packet comprising the data and the data error detection code. The packet does not include the virtual sequence number which is used for calculating error detection. The first communication device transmits the packet to a second communication device.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: August 7, 2018
    Assignee: LSIS CO., LTD.
    Inventors: Sung Han Lee, Dae Hyun Kwon, Joon Seok Oh
  • Patent number: 10026681
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, a first encapsulant encapsulating at least portions of the first connection member and the semiconductor chip, a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip. The fan-out semiconductor package may have excellent rigidity, may be thinned, and may be manufactured in a simplified process.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 17, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae Ho Ko, Dae Hee Lee, Bong Soo Kim, Myeong Ho Hong, Do Young Jeong, Joon Seok Oh