Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

Abstract: An integrated circuit is provided which includes a physically unclonable function (PUF). The integrated circuit comprises a PUF block including a plurality of physically unclonable function (PUF) cells configured to output a cell signal having a unique value according to an input, a conversion unit is configured to receive the cell signal as input, convert the cell signal, and output a conversion signal. A select signal generator provides a first selection signal to the conversion unit. A key generator is configured to receive the conversion signal from the conversion unit and generate a security key therefrom, wherein the conversion unit includes a first layer which outputs a second signal obtained by converting a provided first signal on the basis of a bit value of the first selection signal.

Abstract: A memory device having an error correction function includes: a memory element including multiple memory cells, a reconfiguration logic unit configured to group input data according to data retention properties of each memory cell in which each of the input data will be stored or group storage data stored in the memory element according to data retention properties of each memory cell in which each of the storage data is stored and arrange each of the input data or each of the storage data grouped by identical retention properties to be adjacent to each other, an error correction encoder configured to apply an error correction encoding algorithm with a different intensity to the grouped input data in each group, and an error correction decoder configured to apply an error correction decoding algorithm corresponding to an intensity applied by the error correction encoder to the grouped storage data in each group.

Abstract: The present invention relates to memory apparatuses and an operating methods using a heterogeneous memory array. An operation method of a memory apparatus using a heterogeneous memory array according to an embodiment of the present invention includes dividing an input bit into at least one data bit according to a mode bit, and writing the divided data bits in each cell of the memory array by using a cell level of the memory array which is configured according to the mode bit.

Abstract: The present invention discloses a chaos nanonet device including a nanonet material having metallic and semiconductive properties dispersed on a substrate and an electrode array composed of a plurality of electrodes that has a selected domain size on the nanonet material, and a PUF security apparatus based on the chaos nanonet device.

Abstract: The present invention relates to memory apparatuses and an operating methods using a heterogeneous memory array. An operation method of a memory apparatus using a heterogeneous memory array according to an embodiment of the present invention includes dividing an input bit into at least one data bit according to a mode bit, and writing the divided data bits in each cell of the memory array by using a cell level of the memory array which is configured according to the mode bit.

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

Abstract: A method of laying out a semiconductor device includes arranging a flip-flop in the semiconductor device, and rearranging the flip-flop to a selected location in the semiconductor device. The flip-flop may be configured to receive a clock from a clock gating cell through a clock line, to receive an input signal through an input line, and to output an output signal through an output line. The flip-flop may be rearranged based on a length of the clock line, the number of times the clock line is toggled per reference time, a length of the input line, a length of the output line, and at least one of: the number of times that the input signal is toggled per the reference time, and the number of times that the output signal is toggled per the reference time.

Abstract: A memory device having an error correction function includes: a memory element including multiple memory cells, a reconfiguration logic unit configured to group input data according to data retention properties of each memory cell in which each of the input data will be stored or group storage data stored in the memory element according to data retention properties of each memory cell in which each of the storage data is stored and arrange each of the input data or each of the storage data grouped by identical retention properties to be adjacent to each other, an error correction encoder configured to apply an error correction encoding algorithm with a different intensity to the grouped input data in each group, and an error correction decoder configured to apply an error correction decoding algorithm corresponding to an intensity applied by the error correction encoder to the grouped storage data in each group.

Abstract: An error check and correction method of a 3D memory include a) storing check bits, which is used for error check and correction of an upper memory among the plurality of the memory layers, in one or more of spare cell arrays of a lower memory layer stacked below the upper memory layer and the upper memory layer; and b) performing error check and correction of the upper memory layer by using the stored check bits, wherein in the 3D memory, there are stacked a plurality of memory layers comprising a memory cell array with a matrix structure consisting of memory cells and a spare cell array with a matrix structure consisting of spare memory cells for replacing a fault memory cell, in which a fault occurs, and the 3D memory comprises a master layer for controlling the plurality of the memory layers.

Abstract: A method of laying out a semiconductor device includes arranging a flip-flop in the semiconductor device, and rearranging the flip-flop to a selected location in the semiconductor device. The flip-flop may be configured to receive a clock from a clock gating cell through a clock line, to receive an input signal through an input line, and to output an output signal through an output line. The flip-flop may be rearranged based on a length of the clock line, the number of times the clock line is toggled per reference time, a length of the input line, a length of the output line, and at least one of: the number of times that the input signal is toggled per the reference time, and the number of times that the output signal is toggled per the reference time.

Abstract: The present invention discloses a chaos nanonet device including a nanonet material having metallic and semiconductive properties dispersed on a substrate and an electrode array composed of a plurality of electrodes that has a selected domain size on the nanonet material, and a PUF security apparatus based on the chaos nanonet device.

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

Abstract: A method of improving an error checking and correction performance of a memory includes replacing a defective column including a defective memory cell of the memory cell array with a spare column of a the spare cell array, wherein the memory cell array includes memory cells in a matrix and the spare cell array includes spare memory cells in a matrix to be replaced for defective memory cells; storing check bits of error correction code in at least one memory cell of the defective column; storing defect information regarding a defect of the defective memory cell; determining whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory, based on the defect information; and performing error checking and correction on the memory using a memory cell selected based on a result of determining whether the at least one memory cell storing the check bits is to be used.

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a plurality of through silicon vias (TSVs) configured to provide paths via which digital signals are transmitted or received; at least one redundant TSV configured to provide a path via which a digital signal to be transmitted or received via a failed TSV with a defect among the plurality of TSVs is transmitted or received; a digital-to-analog converter (DAC) configured to convert a digital signal transmitted via the at least one redundant TSV into an analog signal; an analog-to-digital converter (ADC) configured to convert an analog signal received via the at least one redundant TSV into a digital signal; and a multilevel modulator configured to perform multilevel modulation on a digital signal transmitted via the at least one redundant TSV.

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

Abstract: Provided is a cross-point memory device including multiple word lines arranged in parallel with each other, multiple bit lines arranged to be orthogonal to the word lines and parallel with each other, and multiple cross-point memory cells electrically connected between the word lines and the bit lines, respectively. Herein, a cross-sectional area of a cross-section perpendicular to a longitudinal direction of the bit lines is formed to be increased as being farther from a first end of the bit lines.

Abstract: An error check and correction method of a 3D memory include a) storing check bits, which is used for error check and correction of an upper memory among the plurality of the memory layers, in one or more of spare cell arrays of a lower memory layer stacked below the upper memory layer and the upper memory layer; and b) performing error check and correction of the upper memory layer by using the stored check bits, wherein in the 3D memory, there are stacked a plurality of memory layers comprising a memory cell array with a matrix structure consisting of memory cells and a spare cell array with a matrix structure consisting of spare memory cells for replacing a fault memory cell, in which a fault occurs, and the 3D memory comprises a master layer for controlling the plurality of the memory layers.

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a plurality of through silicon vias (TSVs) configured to provide paths via which digital signals are transmitted or received; at least one redundant TSV configured to provide a path via which a digital signal to be transmitted or received via a failed TSV with a defect among the plurality of TSVs is transmitted or received; a digital-to-analog converter (DAC) configured to convert a digital signal transmitted via the at least one redundant TSV into an analog signal; an analog-to-digital converter (ADC) configured to convert an analog signal received via the at least one redundant TSV into a digital signal; and a multilevel modulator configured to perform multilevel modulation on a digital signal transmitted via the at least one redundant TSV.

Abstract: A method of improving an error checking and correction performance of a memory includes replacing a defective column including a defective memory cell of the memory cell array with a spare column of a the spare cell array, wherein the memory cell array includes memory cells in a matrix and the spare cell array includes spare memory cells in a matrix to be replaced for defective memory cells; storing check bits of error correction code in at least one memory cell of the defective column; storing defect information regarding a defect of the defective memory cell; determining whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory, based on the defect information; and performing error checking and correction on the memory using a memory cell selected based on a result of determining whether the at least one memory cell storing the check bits is to be used.