Abstract: A method of forming nonvolatile memory devices according to example embodiments of the present invention includes forming a device isolation layer defining active regions in a semiconductor substrate; forming a plurality of transistors on the active regions, the plurality of transistors comprising a pair of adjacent string selection transistors, a pair of adjacent ground selection transistors, and a plurality of memory cell transistors connected in series between the string selection transistors and ground selection transistors; forming a common source line using SEG between a pair of adjacent ground selection transistors so that the common source line has a top surface lower than a top surface of the pair of adjacent ground selection transistors.

Abstract: A loadless static random access memory (SRAM) may have transfer transistors with at least two threshold voltages. In some embodiments, the transfer transistors may have gate structures with different portions that produce electric fields in different directions. In some embodiments the transfer gate structures may extend down the sidewalls of an active region. In other embodiments, the transfer transistors may have gate structures with different portions that have different gate lengths.

Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 ? in the impurity region.

Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 ? in the impurity region.

Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 ? in the impurity region.

Abstract: A loadless static random access memory (SRAM) may have transfer transistors with at least two threshold voltages. In some embodiments, the transfer transistors may have gate structures with different portions that produce electric fields in different directions. In some embodiments the transfer gate structures may extend down the sidewalls of an active region. In other embodiments, the transfer transistors may have gate structures with different portions that have different gate lengths.

Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.

Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.

Abstract: A clamping wafer holder for chemical-mechanical planarization (“CMP”) machines is provided. It comprises a plate having a surface for receiving on it the wafer, and a retainer around the surface. The retainer includes at least two jaws shaped and arranged such that they define a recess with the surface. The wafer is placed in the recess. An actuator is coupled with the retainer and adjusts it from an open position where the jaws are separated from each other, to a closed position where the jaws clamp an edge portion of the wafer. When the retainer is in the closed position the jaws preferably contact each other and define a continuous cylindrical inner surface. The surface can have a stopper that engages a flat zone of a wafer. Where the shape of the jaws does not match exactly the periphery of the wafer, elastic inserts are mounted on the jaws. A vacuum source is coupled with the plate, to hold the wafer in the holder during reorientation.

Abstract: The present invention provides a method of forming a semiconductor device spacer. In the method, a gate pattern is formed on a semiconductor substrate, and a first insulation layer, a second insulation layer, and a third insulation layer are sequentially formed over substantially the entire surface of the resultant structure. The second and third insulation layers are formed of the same material under a first pressure and a second pressure higher than the first pressure, respectively, and preferably of silicon nitride, using a low pressure chemical vapor deposition (LPCVD) technique. The third and second insulation layers are sequentially, anisotropically etched until the first insulation layer is exposed, thereby forming a spacer and a second insulation pattern. The spacer is selectively removed by an isotropic etching method, to minimize the recessed extent of the second insulation pattern. The exposed first insulation layer is etched to form a first insulation pattern.

Abstract: A method for forming an isolation trench in a semiconductor substrate is provided. An isolation trench is formed in a semiconductor substrate using a trench etch mask pattern. Sidewall spacers are formed on the sidewalls of the trench. A nitride liner is formed over the sidewall spacers. The trench is filled with a trench isolation material. Because the nitride liner is protected, for example, by the sidewall spacers, the formation of a dent in the nitride liner can be prevented.

Abstract: The present invention provides a method of forming a semiconductor device spacer. In the method, a gate pattern is formed on a semiconductor substrate, and a first insulation layer, a second insulation layer, and a third insulation layer are sequentially formed over substantially the entire surface of the resultant structure. The second and third insulation layers are formed of the same material under a first pressure and a second pressure higher than the first pressure, respectively, and preferably of silicon nitride, using a low pressure chemical vapor deposition (LPCVD) technique. The third and second insulation layers are sequentially, anisotropically etched until the first insulation layer is exposed, thereby forming a spacer and a second insulation pattern. The spacer is selectively removed by an isotropic etching method, to minimize the recessed extent of the second insulation pattern. The exposed first insulation layer is etched to form a first insulation pattern.

Abstract: A method for forming an isolation trench in a semiconductor substrate is provided. An isolation trench is formed in a semiconductor substrate using a trench etch mask pattern. Sidewall spacers are formed on the sidewalls of the trench. A nitride liner is formed over the sidewall spacers. The trench is filled with a trench isolation material. Because the nitride liner is protected, for example, by the sidewall spacers, the formation of a dent in the nitride liner can be prevented.

Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.

Abstract: A clamping wafer holder for chemical - mechanical planarization ("CMP") machines is provided. It comprises a plate having a surface for receiving on it the wafer, and a retainer around the surface. The retainer includes at least two jaws shaped and arranged such that they define a recess with the surface. The wafer is placed in the recess. An actuator is coupled with the retainer and adjusts it from an open position where the jaws are separated from each other, to a closed position where the jaws clamp an edge portion of the wafer. When the retainer is in the closed position the jaws preferably contact each other and define a continuous cylindrical inner surface. The surface can have a stopper that engages a flat zone of a wafer. Where the shape of the jaws does not match exactly the periphery of the wafer, elastic inserts are mounted on the jaws. A vacuum source is coupled with the plate, to hold the wafer in the holder during reorientation. The actuator is advantageously operated by the vacuum source.