Abstract: A system, apparatus and method are provided for discerning a host interface, the method including connecting a pull resistor to the interface, sequentially applying a pull voltage to the pull resistor, measuring a loaded electrical characteristic of the interface while the sequentially applied pull voltage is applied to the pull resistor, comparing the loaded electrical characteristic with a predetermined value, and identifying a specification of the interface in accordance with the comparison.

Abstract: An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: A method and apparatus for managing digital rights of a portable storage device are provided. The method comprises a device performing authentication together with the portable storage device and sharing an encryption key with the portable storage device as a result of the authentication, requesting a rights object list from the portable storage device, receiving the rights object list from the portable storage device, and processing and displaying the rights object list.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: A microcontroller for securing data. The microcontroller may be included within a system. The microcontroller reads first and second data from first and second storages, respectively. The microcontroller compares the read first and second data. The microcontroller permits execution of a command based on a result of the comparison.

Abstract: In an inverse calculation circuit, an inverse calculation method, and a storage medium encoded with a computer readable computer program code, a random number generator generates a first random number and a second random number; and an inverter receives a plurality of first bits expressing a first element of a finite field(s) as first inputs, receives a plurality of second bits expressing a second element of a finite field(s) as second inputs. In response to the first and second random numbers, the inverter outputs a plurality of third bits expressing the inverse elements of the first element. The first random number prevents a different power analysis (DPA) decryption attack, and the second random number prevents a timing decryption attack.

Abstract: A method of reducing power consumption and/or enhancing computation speed in the modulus multiplication operation of a Montgomery modulus multiplication module. A coding scheme reduces the need for an adder or memory element for obtaining multiple modulus values, and the use of carry save addition with carry propagation addition enhances the computational speed of the multiplication module.

Abstract: A semiconductor memory device according to some embodiments includes a random converter that receives data and address information including a start address value and an end address value of the address from a central processing unit (CPU), generates and stores at least one random number for each address value from the start address value to the end address value, performs a logical operation on the random number and the data corresponding to the address, and responsively generates randomized data to be stored in memory. Accordingly, the semiconductor memory device randomizes a power consumption signature that can occur when data is stored, thereby writing and reading data in a manner that is resistant to a power attack.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: A memory device including a connector for independently interfacing a host and memory devices using a multimedia card (MMC) protocol is provided. The memory device includes an internal bus and a connector. The internal bus is configured to receive a command or data from the host via a plurality of input/output pins. The connector is electrically connected with the internal bus and connected with another memory device, which interfaces with the host through the internal bus using the MMC protocol.

Abstract: An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: A method and apparatus for resetting a memory card having a plurality of interfaces and a plurality of function blocks, wherein each function block may be associated with a corresponding interface, may include detecting a reset signal for a selected interface of the plurality of interfaces, and interrupting a function block associated with the selected interface. When the selected interface is the only active interface, all function blocks in the memory card may be reset. If interfaces other than the selected interface are active, only the selected interface may be reset.

Abstract: A system, apparatus and method are provided for discerning a host interface, the system including a host having at least one interface, a device in signal communication with the at least one interfaces an interface identifier for identifying a specification of the at least one interface, the interface identifier having at least one electrical characteristic sensor in signal communication with the at least one interface, at least two switches coupled to the at least one interface, each switch in signal communication with a corresponding pull resistor coupled to a pull voltage, and a selectable device interface in signal communication with the host for communicating with the host in response to the electrical characteristic sensor the apparatus including an interface identifier having at least two switches coupled to an interface, each switch in signal communication with a corresponding pull resistor coupled to a pull voltage; and the method including connecting at least one pull resistor to the interface, sequ

Abstract: An integrated circuit card system and method are disclosed. The integrated circuit card system may include a host and a memory card for storing test data transferred from the host. The host may transfer the test data to the memory card when a processing time of the memory card exceeds a reference time. The memory card may calculate the test data transferred from the host, and the host may read out the calculated test data.

Abstract: An example embodiment of the present invention relates to a method of executing a logic operation while remaining safe from side channel attacks. Another example embodiment of the present invention relates to a logic circuit and device for executing a logic operation while remaining safe from side channel attacks.

Abstract: In an inverse calculation circuit, an inverse calculation method, and a storage medium encoded with a computer readable computer program code, a random number generator generates a first random number and a second random number; and an inverter receives a plurality of first bits expressing a first element of a finite field(s) as first inputs, receives a plurality of second bits expressing a second element of a finite field(s) as second inputs. In response to the first and second random numbers, the inverter outputs a plurality of third bits expressing the inverse elements of the first element. The first random number prevents a different power analysis (DPA) decryption attack, and the second random number prevents a timing decryption attack.

Abstract: A microcontroller for securing data. The microcontroller may be included within a system. The microcontroller reads first and second data from first and second storages, respectively. The microcontroller compares the read first and second data. The microcontroller permits execution of a command based on a result of the comparison.

Abstract: An IC card and an IC card system are disclosed in which command processing performance is improved by storing current state data related to a first command upon interruption of an execution cycle for the first command by a second command. Upon completion of the second command, the current state information is reloaded and execution of the first command is resumed.