Patents by Inventor Joong Sik Kim
Joong Sik Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240123793Abstract: A vehicular air conditioning system includes a compressor configured to compress a gaseous refrigerant to have a high temperature and a high pressure while an output rotation speed thereof is variably controlled according to a cooling load in a vehicle interior, and a compressor performance deterioration determination part configured to determine whether or not the performance of the compressor has deteriorated according to the magnitude of a difference between an amount of work (W) of the compressor and an amount of power consumption (kW) of the compressor.Type: ApplicationFiled: April 26, 2022Publication date: April 18, 2024Inventors: Jun Min LEE, Yong Sik KIM, Chan Young LEE, Joong Man HAN
-
Patent number: 11911733Abstract: A hair dye dispenser according to an embodiment of the present invention includes a housing having an opening hole formed on one side of which a hair dye is provided, a plurality of cartridges disposed inside the housing and accommodating at least one dyeing material, a main body in which the plurality of cartridges are rotatably disposed, a main motor for rotating the main body so that a first cartridge of the plurality of cartridges is located adjacent to the opening hole, a discharge module for discharging the dyeing material contained in the first cartridge, and an accommodating body in which a basket accommodating the dyeing material discharged by the discharge module is placed, wherein the discharge module may include an elevating body that pressurizes the first cartridge when moving up and is separated from the first cartridge when moving down.Type: GrantFiled: October 24, 2019Date of Patent: February 27, 2024Assignee: LG FAROUK CO.Inventors: Kyung Sik Jang, Jeong Ho Lee, Jung Yong Lee, Seong Lok Hwang, Sang Min Lee, Joong Hun Kim
-
Publication number: 20240008284Abstract: A semiconductor device according to an embodiment includes a substrate, a bit line and a source line extending in a vertical direction substantially perpendicular to a surface of the substrate, a semiconductor layer disposed between the source line and the bit line on a plane substantially parallel to the surface of the substrate, a non-ferroelectric layer pattern disposed on the semiconductor layer, a floating electrode layer pattern disposed on the non-ferroelectric layer pattern, a ferroelectric layer pattern disposed on the floating electrode layer pattern, and a word line disposed on the ferroelectric layer pattern. An overlap area between the floating electrode layer pattern and the non-ferroelectric layer pattern in the vertical direction is greater than an overlap area between the ferroelectric layer pattern and the word line in the vertical direction.Type: ApplicationFiled: December 9, 2022Publication date: January 4, 2024Inventor: Joong Sik KIM
-
Publication number: 20220385817Abstract: An image processing device is provided. The image processing device includes an image signal processor for processing a raw image received from a camera and a memory for storing a previous frame of the raw image and an intermediate image generated by the processing, wherein the image signal processor estimates an initial global motion vector between the previous frame and a current frame, receives focus region information in the raw image, divides the raw image into a foreground (FG) region and a background (BG) region based on the focus region information, generates a final global motion vector by divisionally updating the initial global motion vector based on the FG region and the BG region, performs motion compensation by applying the final global motion vector to the previous frame, and outputs a final image by blending the motion-compensated previous frame with the current frame.Type: ApplicationFiled: March 14, 2022Publication date: December 1, 2022Inventors: Ho June LEU, Joong Sik KIM, Dong Yeob SHIN, Yeong Min LEE, Hoon JO
-
Patent number: 11166005Abstract: A three-dimensional information acquisition system using pitching practice, and a method for calculating camera parameters are disclosed. The method by which a server calculates camera parameters in order to obtain three-dimensional information, according to various embodiments of the present invention, can comprise the steps of: receiving, from at least two camera devices, image information of dynamic objects moving at a predetermined speed; confirming location information of each dynamic object, included in the image information, on the basis of the same time in each piece of image information received from each camera device; and calculating camera parameters, which indicate the relationship between the camera devices, by using at least a part of each piece of confirmed location information as a corresponding point.Type: GrantFiled: October 27, 2017Date of Patent: November 2, 2021Assignee: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITYInventors: Whol-Yul Kim, Joong-Sik Kim, Je Yeon Kim, Hong Jun Lee
-
Patent number: 10861878Abstract: In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.Type: GrantFiled: October 24, 2019Date of Patent: December 8, 2020Assignee: SK hynix Inc.Inventors: Hyangkeun Yoo, Joong Sik Kim
-
Publication number: 20200351488Abstract: A three-dimensional information acquisition system using pitching practice, and a method for calculating camera parameters are disclosed. The method by which a server calculates camera parameters in order to obtain three-dimensional information, according to various embodiments of the present invention, can comprise the steps of: receiving, from at least two camera devices, image information of dynamic objects moving at a predetermined speed; confirming location information of each dynamic object, included in the image information, on the basis of the same time in each piece of image information received from each camera device; and calculating camera parameters, which indicate the relationship between the camera devices, by using at least a part of each piece of confirmed location information as a corresponding point.Type: ApplicationFiled: October 27, 2017Publication date: November 5, 2020Inventors: Whol-Yul KIM, Joong-Sik KIM, Je Yeon KIM, Hong Jun LEE
-
Publication number: 20200066756Abstract: In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.Type: ApplicationFiled: October 24, 2019Publication date: February 27, 2020Inventors: Hyangkeun YOO, Joong Sik KIM
-
Patent number: 10515698Abstract: The ferroelectric memory device includes a substrate having a base doped region doped with a dopant of a first conductivity type and a trench disposed in the base doped region having an inner wall with a bottom and sidewalls. Also, the ferroelectric memory device includes a ferroelectric gate insulation layer, disposed along the inner wall of the trench, a gate electrode layer disposed on the ferroelectric gate insulation layer inside the trench, and a source region and a drain region, disposed in the substrate at respective ends of the trench and doped with a dopant of a second conductivity type. The ferroelectric memory device also includes a conductive well region, doped with a dopant of the second conductivity type. The conductive well region is disposed in the base doped region and spaced apart from the ferroelectric gate insulation layer.Type: GrantFiled: January 31, 2018Date of Patent: December 24, 2019Assignee: SK hynix Inc.Inventor: Joong Sik Kim
-
Patent number: 10490571Abstract: In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.Type: GrantFiled: May 9, 2018Date of Patent: November 26, 2019Assignee: SK hynix Inc.Inventors: Hyangkeun Yoo, Joong Sik Kim
-
Patent number: 10475814Abstract: A ferroelectric memory device includes a substrate, an interfacial insulation layer disposed on the substrate, a recombination induction layer disposed on the interfacial insulation layer, a ferroelectric layer disposed on the recombination induction layer, and a gate electrode disposed on the ferroelectric layer. The recombination induction layer includes a material containing holes acting as a majority carrier.Type: GrantFiled: June 15, 2018Date of Patent: November 12, 2019Assignee: SK hynix Inc.Inventors: Hyangkeun Yoo, Joong Sik Kim
-
Patent number: 10283184Abstract: Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a ferroelectric memory element including a field effect transistor having a ferroelectric gate dielectric layer and a drain electrode. The nonvolatile memory device also includes a resistive memory element electrically connected in series to the drain electrode of the field effect transistor. A multilevel signal is stored in the nonvolatile memory device according to a channel resistance of the ferroelectric memory element and a resistance of the resistive memory element.Type: GrantFiled: June 23, 2017Date of Patent: May 7, 2019Assignee: SK HYNIX INC.Inventor: Joong Sik Kim
-
Publication number: 20190019800Abstract: A ferroelectric memory device includes a substrate, an interfacial insulation layer disposed on the substrate, a recombination induction layer disposed on the interfacial insulation layer, a ferroelectric layer disposed on the recombination induction layer, and a gate electrode disposed on the ferroelectric layer.Type: ApplicationFiled: June 15, 2018Publication date: January 17, 2019Inventors: Hyangkeun YOO, Joong Sik KIM
-
Publication number: 20180350837Abstract: In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.Type: ApplicationFiled: May 9, 2018Publication date: December 6, 2018Inventors: Hyangkeun YOO, Joong Sik KIM
-
Publication number: 20180277212Abstract: The ferroelectric memory device includes a substrate having a base doped region doped with a dopant of a first conductivity type and a trench disposed in the base doped region having an inner wall with a bottom and sidewalls. Also, the ferroelectric memory device includes a ferroelectric gate insulation layer, disposed along the inner wall of the trench, a gate electrode layer disposed on the ferroelectric gate insulation layer inside the trench, and a source region and a drain region, disposed in the substrate at respective ends of the trench and doped with a dopant of a second conductivity type. The ferroelectric memory device also includes a conductive well region, doped with a dopant of the second conductivity type. The conductive well region is disposed in the base doped region and spaced apart from the ferroelectric gate insulation layer.Type: ApplicationFiled: January 31, 2018Publication date: September 27, 2018Inventor: Joong Sik KIM
-
Patent number: 10079247Abstract: Disclosed is a method of manufacturing a nonvolatile memory device. In the method, a stacked structure is formed on a conductive substrate structure. The stacked structure includes at least one interlayer insulating layer and at least one sacrificial layer alternately stacked with the at least one interlayer insulating layer. A first trench is formed to extend through the stacked structure and to expose the conductive substrate structure. A first gate electrode layer, a dielectric structure, and a channel layer are formed on a side wall of the first trench, the dielectric structure including a ferroelectric layer. At least one recess is formed to expose a side wall of the first gate electrode layer by removing the at least one sacrificial layer. At least one second gate electrode layer is formed by filling the at least one recess with a conductive layer.Type: GrantFiled: June 23, 2017Date of Patent: September 18, 2018Assignee: SK HYNIX INC.Inventor: Joong Sik Kim
-
Publication number: 20180130823Abstract: Disclosed is a method of manufacturing a nonvolatile memory device. In the method, a stacked structure is formed on a conductive substrate structure. The stacked structure includes at least one interlayer insulating layer and at least one sacrificial layer alternately stacked with the at least one interlayer insulating layer. A first trench is formed to extend through the stacked structure and to expose the conductive substrate structure. A first gate electrode layer, a dielectric structure, and a channel layer are formed on a side wall of the first trench, the dielectric structure including a ferroelectric layer. At least one recess is formed to expose a side wall of the first gate electrode layer by removing the at least one sacrificial layer. At least one second gate electrode layer is formed by filling the at least one recess with a conductive layer.Type: ApplicationFiled: June 23, 2017Publication date: May 10, 2018Inventor: Joong Sik KIM
-
Publication number: 20180114560Abstract: Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a ferroelectric memory element including a field effect transistor having a ferroelectric gate dielectric layer and a drain electrode. The nonvolatile memory device also includes a resistive memory element electrically connected in series to the drain electrode of the field effect transistor. A multilevel signal is stored in the nonvolatile memory device according to a channel resistance of the ferroelectric memory element and a resistance of the resistive memory element.Type: ApplicationFiled: June 23, 2017Publication date: April 26, 2018Inventor: Joong Sik KIM
-
Patent number: 9543358Abstract: This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes a transistor comprising a gate where at least a portion of the gate is filled in a semiconductor substrate including an active region defined by an isolation layer; a junction which is disposed over the active region at both side of the gate and includes a metal-containing layer and a first semiconductor layer doped with an impurity and interposed between the active region and the metal-containing layer; and a material layer which is interposed between the junction and the active region to prevent diffusion of the impurity from the first semiconductor layer and defines an opening for coupling the junction to the active region.Type: GrantFiled: July 25, 2014Date of Patent: January 10, 2017Assignee: SK hynix Inc.Inventor: Joong-Sik Kim
-
Publication number: 20150249154Abstract: This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes a transistor comprising a gate where at least a portion of the gate is filled in a semiconductor substrate including an active region defined by an isolation layer; a junction which is disposed over the active region at both side of the gate and includes a metal-containing layer and a first semiconductor layer doped with an impurity and interposed between the active region and the metal-containing layer; and a material layer which is interposed between the junction and the active region to prevent diffusion of the impurity from the first semiconductor layer and defines an opening for coupling the junction to the active region.Type: ApplicationFiled: July 25, 2014Publication date: September 3, 2015Inventor: Joong-Sik Kim