Abstract: Trace recording based on recording an influx to a lower-level cache by reference to prior log data, based on knowledge of an upper-level cache. A computing device includes a plurality of processing units, a plurality of N-level caches, and an (N+i)-level cache that is a backing store for the N-level caches. Based on activity of a first processing unit, the computing device detects an influx of data to a first N-level cache. The computing device checks the (N+i)-level cache to determine if the data was already logged for a second processing unit. Based on the check, the computing device (i) causes the data to be logged for the first processing unit by reference to log data (i.e., when the data was already logged), or causes the data to be logged by value for the first processing unit (i.e., when the data was not already logged).

Abstract: Trace recording based on data influxes to an outer-level cache and cache coherence protocol (CCP) transitions between inner caches. Example computing device(s) include a plurality of processing units, a plurality of (N-1)-level caches, and an N-level cache that is associated with two or more of the (N-1)-level caches and that is a backing store for the two or more (N-1)-level caches. Based at least on detecting influx(es) of data to a location in the N-level cache during execution across the processing units, the computing device(s) causes the influx(es) of data to be logged. The computing device(s) also causes one or more (N-1)-level CCP transitions between the two or more (N-1)-level caches to be logged. The (N-1)-level CCP transitions result from the location being accessed by two or more of the processing units.

Abstract: Facilitating recording a trace of code execution using a processor cache. A method includes identifying an operation by a processing unit on a line of the cache. Based on identifying the operation, accounting bits for the cache line are set. Setting the accounting bits includes (i) setting the accounting bits to a reserved value when the operation is a write and tracing is disabled, (ii) setting the accounting bits to an index of the processing unit when the operation is a write and the accounting bits for the cache line are set to a value other than the index of the processing unit, or (iii) setting the accounting bits to the index of the processing unit when the operation is a read that is consumed by the processing unit and the accounting bits for the cache line are set to a value other than the index of the processing unit.

Abstract: A code entity of an application, for which a differential analysis is to be performed, is identified in a replayable trace of a prior execution of the application. A prior invocations of the code entity are replayed by re-executing executable instructions of the code entity based on the replayable trace. Based on the replay, a families of invocations of the code entity are identified. Each family is defined based upon attributes that identify at least one class of runtime behavior of the code entity that is observed during the replay of the invocations of the code entity. First attributes of a first family that substantially contribute to classifying a first class of invocations of the code entity within the first family are identified, and second attributes of a second family that substantially contribute to classifying a second class of invocations of the code entity within the second family are identified.

Abstract: Embodiments relate to a virtualization layer capturing replayable execution traces of VMs managed by the virtualization layer. Execution tracing can be performed on any unit of execution managed by the virtualization layer, e.g., threads, processes, virtual processors, individual VMs, multiple VMs, etc. Traced execution units may be executing in parallel. Execution tracing involves capturing to a buffer: executed instructions, memory inputted to instructions, memory outputted by instructions, registers touched by instructions, and ordering markers. Trace data can be captured in chunks, where causality is preserved and ordering is preserved between chunks but not necessarily within chunks. The chunks may be delineated by inserting monotonically increasing markers between context switches, thus relatively ordering the chunks. Determinism may be partially provided by identifying non-deterministic events. VM tracing may be transparent to guest software, which need not be instrumented.

Abstract: Decoupling trace data streams using cache coherence protocol (CCP) data. One or more trace data streams include cache activity trace data and CCP trace data relating to executing a plurality of threads. The cache activity trace data includes inter-thread data dependencies comprising dependent cache activity trace entries, which each record a corresponding memory access by a corresponding thread in reliance on traced CCP dependence between threads. The inter-thread data dependencies are removed to create independent cache activity trace data for each of the plurality of threads that enables each thread to be replayed independently. The removal includes, for each dependent cache activity trace entry (i) identifying a corresponding value of the corresponding memory access by the corresponding thread based on the traced CCP dependence between threads, and (ii) recording the corresponding value of the corresponding memory access on behalf of the corresponding thread.

Abstract: Detecting and providing notice of non-faulting memory accesses during prior execution of an application based on a replay-able trace of the application's execution. Embodiments include replaying portion(s) of prior execution of the application from a replay-able trace the application's prior execution, while tracking lifetime of memory region(s) used by the application. Based on tracking lifetime of the memory region, non-faulting but improper memory access(es) by the application during its prior execution are detected. Notification of these non-faulting but improper memory access(es) are provided at a user interface and/or to a software component.

Abstract: Efficient breakpoint detections via caches comprises monitoring a memory location by detecting cache misses on a cache. Embodiments include identifying a memory address that is to be monitored, storing the memory address in a breakpoint monitoring list, and ensuring that any cache lines overlapping with the memory address are evicted from a cache. Based at least on an indication of an occurrence of a cache miss, embodiments determine whether a portion of a cache line imported into the cache based on the cache miss overlaps with the memory address stored in the breakpoint monitoring list. When the portion of the imported cache line does overlap with the memory address, embodiments process one or more monitoring operations on the memory address, and, based on the memory address being stored in the breakpoint monitoring list, embodiments evict the imported cache line from the cache.

Abstract: Facilitating recording a trace of code execution using way-locking in a set-associative processor cache. A computing device reserves cache line(s) in set(s) of cache lines of a set-associative cache for caching only locations in the system memory that are allocated to a particular executable entity. During a traced execution of the particular executable entity, the computing device detects that a cache miss has occurred on a location in the system memory that is allocated to a particular executable entity, and that a value at the location of system memory is being cached into one of the reserved cache lines. Based on the value at the location of system memory being cached into a reserved cache line, the computing device logs into a trace data stream at least a portion of the value at the location of system memory being cached into the reserved cache line.

Abstract: Embodiments relate to a virtualization layer capturing replayable execution traces of VMs managed by the virtualization layer. Execution tracing can be performed on any unit of execution managed by the virtualization layer, e.g., threads, processes, virtual processors, individual VMs, multiple VMs, etc. Traced execution units may be executing in parallel. Execution tracing involves capturing to a buffer: executed instructions, memory inputted to instructions, memory outputted by instructions, registers touched by instructions, and ordering markers. Trace data can be captured in chunks, where causality is preserved and ordering is preserved between chunks but not necessarily within chunks. The chunks may be delineated by inserting monotonically increasing markers between context switches, thus relatively ordering the chunks. Determinism may be partially provided by identifying non-deterministic events. VM tracing may be transparent to guest software, which need not be instrumented.

Abstract: Querying resource lifetime using a trace of program execution. An embodiment includes identifying a query expression targeted at least a portion of the trace of program execution. The query expression specifies at least (i) a data object representing a plurality of events identified in the trace, each event associated with one or more attributes relating to resource lifetime, and (ii) one or more conditions matching the one attributes relating to resource lifetime. In response to receiving the query expression, the query expression is processed based at least on an analysis of an identified subset of the trace. Based on processing the query expression, a result data set that includes or identifies at least one of the plurality of events that meets the one or more conditions is presented.

Abstract: Facilitating recording a trace file of code execution using a processor cache. A computing device includes a plurality of processing units and a processor cache shared by the plurality of processing units. The processor cache includes a set of accounting bits that include different pluralities of accounting bits. Each plurality of accounting bits is associated with a different cache line of a plurality of cache lines of the processor cache, and includes a different unit bit associated with a different one of the plurality of processing units. The computing device also includes control logic that is configured to use the pluralities of accounting bits to indicate, for each cache line and for each processing unit, whether or not the processing unit has logged into a trace file a current value stored in the value portion of the cache line.

Abstract: Facilitating recording a trace file of code execution using a processor cache. A method includes identifying an operation by a processing unit on a line of the cache. Based on identifying the operation, index bits for the cache line are set. Setting the index bits includes one of: (i) setting the bits to a reserved value when the operation is a write operation and tracing is disabled, (i) setting the bits to an index of the processing unit when the operation is a write operation and the bits are already set to a value other than the index of the processing unit, or (iii) setting the bits to the index of the processing unit when the operation is a read operation that is consumed by the processing unit and the bits are already set to a value other than the index of the processing unit.

Abstract: Distributed trace recording and replay is based on tracing execution of a first entity at a first computer system, while also concurrently and independently tracing execution of a second entity at a second computer system. The traces include corresponding orderable events that occurred during execution of the entities at their corresponding computer systems, and are recorded at fidelity that enables complete replay of the recorded execution of the entities. Each trace includes information that at least partially orders, among the respective orderable events, sending or receipt of at least one message passed between the entities.

Abstract: Presenting differences between code entity invocations includes identifying a plurality of families of invocations of a code entity. Each family is defined based upon a plurality of attributes that identify a class of runtime behavior of the code entity. First attribute(s) of a first family are identified. These first attribute(s) substantially contributed to classifying a first class of invocations of the code entity within the first family. Similarly, second attribute(s) of a second family are identified. These second attribute(s) substantially contributed to classifying a second class of invocations of the code entity within the second family. Differences between at least two invocations of the code entity are presented, based on differences between the one or more first attributes and the one or more second attributes.

Abstract: Efficient breakpoint detections via caches comprises monitoring a memory location by detecting cache misses on a cache. A memory address that is to be monitored is stored in a monitoring list, and any cache line overlapping with the memory address is evicted if it exists in a cache. When the occurrence of a cache miss based on a memory access operation is detected, a determination is made as to whether a portion of a cache line imported into the cache based on the cache miss overlaps with the memory address stored in the monitoring list. When there is an overlap, one or more monitoring operations are processed on the memory address, and the imported cache line is evicted from the cache.

Abstract: Performing a cache-based trace recording using cache coherence protocol (CCP) data. Embodiments detect that an operation that causes an interaction between a cache line and a backing store has occurred, that logging is enabled for a processing unit that caused the operation, that the cache line is a participant in logging, and that the CCP indicates that there is data to be logged to a trace. Embodiments then cause that data to be logged to the trace, which data is usable to replay the operation.

Abstract: Creating key frames during indexing of a trace for responsive trace replay. A method includes identifying responsiveness goal(s) for trace replay, including identifying a target trace section replay time. A portion of execution of executable entit(ies) is replayed based on trace data stream(s). While replaying execution of the executable entit(ies), and based on the identified target trace section replay time, points of interest in execution of the executable entit(ies) are identified. At least one key frame is created for each of the identified plurality of points of interest. Each key frame enables replay of at least one of the one or more executable entities beginning at the key frame.

Abstract: Methods and systems are disclosed for debugging program code at instruction level by emulating an epilog. Issues with retrieving values that a caller function has stored in non-volatile registers before calling a callee function are addressed at the instruction code level by through emulation. The epilog of the callee function may be emulated after copying a computing environment of the target program code from a target system to an emulation system. When the debugged code does not include an epilog, values that a caller function stored before calling a callee function in non-volatile registers may be retrieved by emulating the calling function forward from the breakpoint.

Abstract: Methods and systems are disclosed for logging trace data generated by executing program code at an instruction level. In aspects, high volumes of trace data are generated during certain time periods, e.g., immediately following a start of the tracing. Processors operating at normal speeds are often unable to log such high volumes of trace data. The issue of such high volumes of trace data may be addressed by selectively and dynamically controlling logging of outstanding trace data. For example, a rate of generating the trace may be reduced by slowing processor speeds, logging of outstanding trace data may be suspended for a period, and logging of non-urgent trace data may be selectively delayed.