Abstract: Described technologies aid execution control during replays of traced program behavior. Cross-level mapping correlates source code, an intermediate representation, and native instructions in a trace. The trace includes a record of native code instructions which were executed by a runtime-managed program. The trace does not include any executing instance of the runtime. Breakpoints are set to align trace locations with source code expressions or statements, and to skip over garbage collection and other code unlikely to interest a developer. A live debugging environment is adapted to support trace-based reverse execution. An execution controller in a debugger or other tool may utilize breakpoint ranges, cross-level mappings, backward step-out support, and other items to control a replay execution of the trace.

Abstract: An emulator can use compiler metadata to efficiently emulate execution of executable machine code compiled from the source code. Based on accessing compiler metadata associated with machine code, an emulator can identify behavior(s) of the source code from which the machine code is compiled which are not implied by the machine code. From these behaviors, the emulator can identify emulator optimization(s) that can be applied, during emulation of execution of a thread, to reduce a number of steps needed to emulate execution the machine code, while preserving any externally-visible side-effects. These optimizations can operate to reduce a number of emulator operations needed emulate execution of the machine code, or to elide one or more machine code instructions from emulation. These optimizations can then be applied while emulating execution of the thread. The emulated execution could be recorded to a trace that is equivalent to a trace recorded without these optimizations.

Abstract: An emulator can use compiler metadata to efficiently emulate execution of executable machine code compiled from the source code. Based on accessing compiler metadata associated with machine code, an emulator can identify behavior(s) of the source code from which the machine code is compiled which are not implied by the machine code. From these behaviors, the emulator can identify emulator optimization(s) that can be applied, during emulation of execution of a thread, to reduce a number of steps needed to emulate execution the machine code, while preserving any externally-visible side-effects. These optimizations can operate to reduce a number of emulator operations needed emulate execution of the machine code, or to elide one or more machine code instructions from emulation. These optimizations can then be applied while emulating execution of the thread. The emulated execution could be recorded to a trace that is equivalent to a trace recorded without these optimizations.

Abstract: Indexing and searching a bit-accurate trace for arbitrary length/arbitrary alignment values in traced thread(s). Indexing includes, while replaying a plurality of trace segments, identifying a set of n-grams for each trace segment that exist in processor data influx(es) and/or store(s) to a processor cache that resulted from replay of the trace segment. An index data structure, which associates each identified n-gram with trace location(s) at or in which the n-gram was found, is then generated. The index data structure thus associates unique n-grams with prior execution time(s) at or during which the traced thread(s) read or wrote the n-gram. Searching an indexed trace includes identifying n-grams in a query and using the index data structure to determine trace location(s) where these n-grams were seen during indexing. A query response is generated after using trace replay to locate particular execution time(s) and memory location(s) at which the n-grams occurred.

Abstract: Storing memory reordering hints into a processor trace includes, while a system executes a plurality of machine code instructions, the system initiating execution of a particular machine code instruction that performs a load to a memory address. Based on initiation of this instruction, a system initiates storing, into the processor trace, a particular cache line in a processor cache that stores a first value corresponding to the memory address. After initiating storing of the particular cache line, and prior to committing the particular machine code instruction, the system detects an event affecting the particular cache line. Based on this detection, the system initiates storing of a memory reordering hint into the processor trace.

Abstract: Tentatively executing an entity includes identifying a runtime data element used by the entity, the runtime data element having a first value at a particular point based on a trace of a prior execution of the entity. Input specifying a second, different, value for the runtime data element is received. A tentative replay of the entity is performed, the tentative replay applying the second, different, value for the runtime data element using the trace. The tentative replay includes setting the runtime data element to the second value and emulating one or more memory writes performed by the entity during the tentative replay. Based on determining that the entity has requested data from the trace during the tentative replay that is not available in the trace, it is detected that the tentative replay has deviated from the prior execution and can no longer continue using the trace.

Abstract: Efficient register breakpoint checks rely on initiating an event based on an access to a register. Initiating the event can include, based on decoding a machine code instruction, identifying one or more registers that a machine code instruction could touch, and inserting an identification of the touched registers into a stream of executable operations for the machine code instruction. Then, while executing the executable operations, these registers can be compared with a register breakpoint collection. An event can be generated when one of these registers is in the register breakpoint collection. The event might trigger a conditional analysis, an execution break, and/or logging. In some implementations, the event might enable lifetime and/or taint analysis by removing a register from a monitoring collection if the executable operations write to the register, or by adding a destination of a read to the monitoring collection if the executable operations read from the register.

Abstract: The disclosure relates to embodiments, implemented at least partially in microcode, that use cache misses to trigger logging to a processor trace. One embodiment relies on tracking bits in a processor cache. During a transition from a non-logged context to a logged context, this embodiment invalidates or evicts cache lines whose tracking bits are not set. When logging, this first embodiment logs during cache misses, and sets tracking bits for logged cache lines. Another embodiment relies on way-locking. This second embodiment assigns first ways to a logged entity and second ways to a non-logged entity. The second embodiment ensures the logged entity cannot read cache lines from the second logging ways by flushing the second way during transitions from non-logging to logging, ensures the logged entity cannot read non-logged cache lines from the first ways, and logs based on cache misses into the first ways while executing a logged context.

Abstract: Trace logging based on an upper cache layer determining how to log an influx by a lower cache layer. A second cache receives, from a lower layer first cache, a logging request referencing a memory address. The second cache determines whether it has a cache line for the memory address. When the cache line is present, the second cache either forwards the request to a next logging cache layer or causes the cache line to be logged if second cache is the outermost logging layer. When the cache line isn't present, the second cache causes the cache line to be logged when the cache line isn't determined by the second cache to be logged, or when it is determined by the second cache to be logged but it is not determined whether the first cache is aware of a current value of the cache line in the second cache.

Abstract: Storing memory reordering hints into a processor trace includes, while a system executes a plurality of machine code instructions, the system initiating execution of a particular machine code instruction that performs a load to a memory address. Based on initiation of this instruction, a system initiates storing, into the processor trace, a particular cache line in a processor cache that stores a first value corresponding to the memory address. After initiating storing of the particular cache line, and prior to committing the particular machine code instruction, the system detects an event affecting the particular cache line. Based on this detection, the system initiates storing of a memory reordering hint into the processor trace.

Abstract: Efficient breakpoint detections via caches comprises monitoring a memory location by detecting cache misses on a cache. Embodiments include identifying a memory address that is to be monitored, storing the memory address in a breakpoint monitoring list, and ensuring that any cache lines overlapping with the memory address are evicted from a cache. Based at least on an indication of an occurrence of a cache miss, embodiments determine whether a portion of a cache line imported into the cache based on the cache miss overlaps with the memory address stored in the breakpoint monitoring list. When the portion of the imported cache line does overlap with the memory address, embodiments process one or more monitoring operations on the memory address, and, based on the memory address being stored in the breakpoint monitoring list, embodiments evict the imported cache line from the cache.

Abstract: Presenting historical state associated with prior execution of an entity. Based on replaying segment(s) of execution of an entity based on a trace, embodiments could present an indication of whether a value of a code element is, at a first execution time point, unknown, known, previously known, and/or known in the future. Additionally, or alternatively, embodiments could present an indication of a value relied upon by simulated execution of a function at a second execution time point, along with an indication of a timing of knowledge of the value in relation to the second execution time point. Additionally, or alternatively, embodiments could present an indication that a return value of a function would be known if the function had executed at a third execution time point, or an indication that the return value would be unknown if the function had executed at the third execution time point.

Abstract: Recording a trace of code execution using reserved cache lines in a cache. A computing device comprises processing units and a cache. The cache includes a first plurality of cache lines that each comprise an address portion for storing a memory address within the memory device, and a value portion for storing a value associated with the memory address. The cache also includes a second plurality of reserved cache lines that store a plurality of sets of accounting bits. Each set of accounting bits comprises a plurality of accounting bits and is associated with a different cache line in the first cache lines. Each cache line in the second cache lines stores multiple of the sets of accounting bits. Stored control logic uses the plurality of sets of accounting bits in the second cache lines to track trace logging information for the first cache lines.

Abstract: Tentatively executing an entity includes performing a first, execution of an entity. At a point in the first execution, the first execution is suspended and input specifying an alternate value for a runtime data element is received. Based on the input, a second execution of the entity is performed starting at the point in the first execution, while enabling the first execution to be later resumed unaffected by the second execution. This second execution includes setting the runtime data element to the alternate value, and emulating one or more memory writes performed by the entity during the second execution. The first execution of the entity could comprise a live execution, an execution that is based on trace data, an execution based on a process dump, etc.

Abstract: Decoupling trace data streams using cache coherence protocol (CCP) data. One or more trace data streams include cache activity trace data and CCP trace data relating to executing a plurality of threads. The cache activity trace data includes inter-thread data dependencies comprising dependent cache activity trace entries, which each record a corresponding memory access by a corresponding thread in reliance on traced CCP dependence between threads. The inter-thread data dependencies are removed to create independent cache activity trace data for each of the plurality of threads that enables each thread to be replayed independently. The removal includes, for each dependent cache activity trace entry (i) identifying a corresponding value of the corresponding memory access by the corresponding thread based on the traced CCP dependence between threads, and (ii) recording the corresponding value of the corresponding memory access on behalf of the corresponding thread.

Abstract: Methods and systems are disclosed for logging trace data generated by executing program code at an instruction level. In aspects, high volumes of trace data are generated during certain time periods, e.g., immediately following a start of the tracing. Processors operating at normal speeds are often unable to log such high volumes of trace data. The issue of such high volumes of trace data may be addressed by selectively and dynamically controlling logging of outstanding trace data. For example, a rate of generating the trace may be reduced by slowing processor speeds, logging of outstanding trace data may be suspended for a period, and logging of non-urgent trace data may be selectively delayed.

Abstract: Recording a memory address includes identifying a first subset of high bits of the memory address, determining that a first value of the first subset equals a second value of a group of high bits already recorded, recording a second subset of low bits of the memory address while refraining from recording the first subset, and setting one or more flag bits to indicate that only the second subset were recorded. Also, recording a memory value includes identifying a plurality of groups of consecutive bits of the memory value, determining that a first group contains bits having a defined pattern and that a second group contains bits lacking the defined pattern, recording the second group while refraining from recording at least a portion of the first group, and setting one or more flag bits to indicate that the first group was not recorded.

Abstract: Described technologies extend the information available from an execution trace of a program by providing heuristically-derived values for memory contents when the trace does not include data expressly showing the value of a memory cell at a particular execution time. Various heuristics are described. The heuristics may use information about the memory cell at other times to produce the derived value. Some heuristics use other trace data, such as whether the memory cell is in a stack, whether there are gaps in the trace, or whether garbage collection or compilation occurred near the time in question. Grounds for the derived value are reported along with the derived value. A time-travel debugger or other program analysis tool can then present the derived values to users, or make other use of the derived values and grounds to assist debugging and other efforts to improve the functioning of a computing system.

Abstract: Protecting sensitive information in connection with a trace of an original execution of an entity. Embodiments include identifying that original information—which was accessed based on an original execution of one or more original executable instructions of the entity—comprises sensitive information. Based on the original information comprising the sensitive information, embodiments include performing one or both of (i) storing first trace data comprising alternative information—rather than the original information, while ensuring that an execution path that was taken by the entity based on the original information is also taken during replay of the original execution of the entity; or (ii) storing second trace data that causes zero or more alternative executable instructions—rather than the one or more original executable instructions of the entity—to be executed during the replay of the original execution of the entity.

Abstract: Performing breakpoint detection via a cache includes detecting an occurrence of a memory access and identifying whether any cache line of the cache matches an address associated with the memory access. When a cache line does match the address associated with the memory access no breakpoint was encountered. When no cache line matches the address associated with the memory access embodiments identify whether any cache line matches the address associated with the memory access when one or more flag bits are ignored. When a cache line does match the address associated with the memory access when the one or more flag bits are ignored, embodiment perform a check for whether a breakpoint was encountered. Otherwise, embodiments process a cache miss.