Abstract: Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of the logic circuit in a manner dependent on a changeover control signal that is applied to a control terminal of the voltage supply switching device; and having (b) a charge equalization switching device which, in a manner dependent on a control switching pulse, connects the supply voltage line of the logic circuit to the control terminal of the voltage supply switching device for the duration of the control switching pulse so that charge equalization is effected between the supply voltage line and the control terminal of the voltage supply switching device in order to generate the changeover control signal.

Abstract: Methods and devices for saving and/or setting a circuit state of a microelectronic circuit that includes at least one scan chain for testing the circuit are disclosed. In this connection, the at least one scan chain is used to save and/or set the circuit state, as a result of which an expansion of the circuit is unnecessary.

Abstract: A semiconductor device detects and adjusts leakage current dependent on threshold voltage of an integrated semiconductor device. To adjust the threshold voltage variation due to uncertainties in the channel length induced by the fabrication process (short channel effect) in the semiconductor a comparison between small and long channel devices is proposed. According to the comparison result, a bias potential is provided to the semiconductor device to adjust the threshold voltage.

Abstract: The coil and coil system is provided for integration in a microelecronic circuit. The coil is placed inside an oxide layer of a chip, and the oxide layer is placed on the substrate surface of a substrate. The coil comprises one or more windings, whereby the winding(s) is/are formed by at least segments of two conductor tracks, which are each provided in spatially spaced-apart metalization levels, and by via-contacts which connect these conductor track(s) and/or conductor track segments. In order to be able to produce high-quality coils, a coil is produced with the largest possible coil cross-section, whereby a standard metalization, especially a standard metalization using copper, can, however, be used for producing the oil. To this end, the via contacts are formed from a stack of two ore more via elements arranged one above the other. Parts of the metalization levels can be located between the via elements.

Abstract: A method of determining the critical path of a circuit includes first determining the paths, their mean path transit times and their path transit time fluctuations. Paths having similar statistical parameters are combined to form one path group. For each path group, a statistical group figure is, then, calculated and, for the totality of paths considered, a statistical total figure is calculated. Finally, the critical paths of the circuit are determined by taking into consideration the total figure, comparing the group figures at or above a critical path transit time Tc.

Abstract: The coil and coil system is provided for integration in a microelecronic circuit. The coil is placed inside an oxide layer of a chip, and the oxide layer is placed on the substrate surface of a substrate. The coil comprises one or more windings, whereby the winding(s) is/are formed by at least segments of two conductor tracks, which are each provided in spatially spaced-apart metalization levels, and by via-contacts which connect these conductor track(s) and/or conductor track segments. In order to be able to produce high-quality coils, a coil is produced with the largest possible coil cross-section, whereby a standard metalization, especially a standard metalization using copper, can, however, be used for producing the oil. To this end, the via contacts are formed from a stack of two ore more via elements arranged one above the other. Parts of the metalization levels can be located between the via elements.

Abstract: In a method for operating an SRAM MOS transistor memory cell, the memory cell comprises a 6-transistor memory cell composed of two inverters with feedback, each of which is connected to a bit line via a selection transistor which is driven by a word line. Both selection transistors are switched on when writing information to the memory cell. Only the first selection transistor is switched on, the other selection transistor remaining switched off, when reading the contents of the cell. In this way, the charge on only one bit line is changed when reading.