Abstract: A network device includes systems and methods for processes streams of data. The network device stores data and addresses corresponding to the streams in a memory. The addresses store pointers to the data. Output logic within the network device determines whether an address is required to be fetched. When no address is required to be fetched, then data is read from the memory. When an address is required to be fetched, the address is fetched from the memory and data is read from the memory using the fetched address. To facilitate this, notifications may be stored corresponding to the streams and notification pointers may be used to identify ones of the notifications to be processed. A prefetch pointer may also be used to identify a notification with one or more associated addresses to be prefetched.

Abstract: An elevator system for controlling movement of an elevator car coupled to a drive to serve floors in a building in response to hall calls generated from a plurality of hall call devices located at floors served by the elevator car, includes a control for generating a velocity pattern signal from stored parameter values representing desired jerk, acceleration and constant speed relative to time. The drive responds to the velocity pattern signal to move the elevator car to the floor associated with each hall call. The control selectively generates a high performance velocity pattern signal and an energy conservation velocity pattern signal in response to parameter values that can be changed by user input. Sensing a predetermined condition such as the application emergency power to the drive and/or a high wind speed automatically modifies the velocity pattern signal.

Abstract: Apparatus and methods for a cache controller to maintain cache consistency in a cache memory structure having a single copy of a cache tag memory while supporting multiple outstanding operations in a multiple processor computer system. The CPU includes a small internal cache memory structure. A substantially larger external cache array is coupled to both the CPU and the CC via first, integrated address and data bus. The CC is in turn coupled to a second bus interconnecting, among other devices, processors, I/O devices, and a main memory. The external cache is subblocked. A cache directory in the CC tracks usage of the external cache. An input buffer in the CC is connected to the first bus to provide buffering of commands sent by the CPUs. An output buffer in the CC is coupled to the second bus for buffering commands directed by the CC to devices operating on the second bus.

Abstract: Apparatus and methods for a cache controller preserving cache consistency and providing multiple outstanding operations in a cache memory structure supporting a high performance central processor unit (CPU). An external cache array is coupled to both the CPU and a cache controller (CC), and is subblocked to reduce miss rate. The CC is coupled via a high speed bus to a main memory. A cache directory in the CC tracks usage of the external cache, and is organized to support a choice of bus protocols for buses intercoupling the CC to the main memory. The cache directory consists of tag entries, each tag entry having an address field and multiple status bit fields, one status bit field for each subblock. The status bit fields, in addition to shared-, owner-, and valid-bits, have a pending-bit which, when set, indicates a pending uncompleted outstanding operation on a subblock, and will prevent the CPU from overwriting the corresponding subblock.

Abstract: A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher clients, each of which is coupled to a separate system bus. The bus allows the cache controller to provide independent processor-side access to the cache and allows the bus watchers to handle functions related to bus-snooping. An arbiter is employed to allow the bus to be multiplexed between the bus watchers and cache controller. Flow control mechanisms are also employed to ensure that queues receiving packets or arbitration requests over the bus never overflow. A default grantee mechanism is employed to minimize the arbitration latency due to a request for the bus when the bus is idle.

Abstract: A high chair bench assembly simultaneously accommodates several children side-by-side on a horizontal bench bottom pivotally connected to a vertical bench back which is attached to a wall. The bench bottom is held in the horizontal position by a support bar pivotally connected at the top of the side of the bench back and which has a keyhole slot brought over a stud located at the front of the side edge of the bench bottom. The bottom is lowered to a vertical stowage position by removing the keyhole slot from the stud. Each seating place is provided with back and bottom cushions as well as a safety belt. Trays are attached at independently selectable heights above the brackets into vertical perforated tracks located at the sides of each seating place. The trays are secured by an adjustable tension tie releasably connecting the front of each tray to an adjacent bench bottom location.