Patents by Inventor Jorge E Caviedes

Jorge E Caviedes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11936915
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20230134137
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: December 28, 2022
    Publication date: May 4, 2023
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 11546639
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20220021906
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 20, 2022
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 11172233
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20210014538
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 10863204
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20200107046
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 10440395
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Patent number: 10360687
    Abstract: Techniques are provided for detection and location of active display regions in videos with static borders. A methodology implementing the techniques according to an embodiment includes extracting features from rows and columns of pixels of a video frame. The features are based on horizontal gradient runs (HGRs) and vertical gradient runs (VGRs). The method also includes detecting one or more static regions of the frame, based on a comparison of differences between the features of the current video frame and features extracted from a previous video frame. The method further includes detecting one or more boundaries of the static regions based on a location of a maximum value of one of the features within the static region, if the maximum value is greater than a boundary detection threshold value. Determination of the active region in the current video frame is based on exclusion of the detected static regions.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Yeongseon Lee, Nilesh A. Ahuja, Mahesh Subedar, Jorge E. Caviedes
  • Patent number: 9940543
    Abstract: A processor computes a measure of input image structural complexity of an input image, and searches a database of true positives to find one or more entries in the database that represent true positive images that are structurally similar to the input image. The processor compares a measure of signal quality of the input image and a measure of signal quality of one of the true positive images, as retrieved from the database, and based on the comparison updates a control variable that configures a signal quality conditioning process that is to be performed on the input image prior to processing of the input image by a computer vision processor thus improving performance of the computer vision task. Other embodiments are also described and claimed.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: April 10, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Sin Lin Wu
  • Publication number: 20180005387
    Abstract: Techniques are provided for detection and location of active display regions in videos with static borders. A methodology implementing the techniques according to an embodiment includes extracting features from rows and columns of pixels of a video frame. The features are based on horizontal gradient runs (HGRs) and vertical gradient runs (VGRs). The method also includes detecting one or more static regions of the frame, based on a comparison of differences between the features of the current video frame and features extracted from a previous video frame. The method further includes detecting one or more boundaries of the static regions based on a location of a maximum value of one of the features within the static region, if the maximum value is greater than a boundary detection threshold value. Determination of the active region in the current video frame is based on exclusion of the detected static regions.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Applicant: INTEL CORPORATION
    Inventors: Yeongseon Lee, Nilesh A. Ahuja, Mahesh Subedar, Jorge E. Caviedes
  • Patent number: 9710890
    Abstract: In some embodiments, color and contrast enhancement video processing may be done in one shot instead of adjusting one of color and contrast enhancement, then the other, and then going back to the first one to readjust because of the second adjustment. In some embodiments, global lightness adjustment, local contrast enhancement, and saturation enhancement may be done at the same time and in parallel. Lightness adjustment improves visibility of details for generally dark or generally light images without changing intended lighting conditions in the original shot, and is used to enhance the range of color/saturation enhancement. Local contrast enhancement done in parallel improves visual definition of objects and textures and thus local contrast and perceived sharpness.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Abhijit Sarkar, Jorge E. Caviedes, Mahesh Subedar
  • Publication number: 20170177977
    Abstract: A processor computes a measure of input image structural complexity of an input image, and searches a database of true positives to find one or more entries in the database that represent true positive images that are structurally similar to the input image. The processor compares a measure of signal quality of the input image and a measure of signal quality of one of the true positive images, as retrieved from the database, and based on the comparison updates a control variable that configures a signal quality conditioning process that is to be performed on the input image prior to processing of the input image by a computer vision processor thus improving performance of the computer vision task. Other embodiments are also described and claimed.
    Type: Application
    Filed: March 7, 2017
    Publication date: June 22, 2017
    Inventors: Jorge E. Caviedes, Sin Lin Wu
  • Patent number: 9641800
    Abstract: Three-dimensional video is presented on a two-dimensional display. The view of the video is driven by user interaction. In one example, a two-dimensional (2D) video sequence in real time with a first view is synthesized from a video image sequence with depth captured by a first device. The 2D video sequence with the first view is provided to a second device in real time. A command is received from the second device to change a view of the 2D video sequence as the video sequence is rendered. The view of the 2D video sequence is changed as it is rendered to a 2D video sequence with a second view, and the 2D video sequence with the second view is provided to the second device in real time.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Sin Lin Wu
  • Patent number: 9621741
    Abstract: Techniques are disclosed to adaptively control an image sensor and image signal processor (ISP), collectively known as an image pipeline, such that a minimum amount of power is consumed by an electronic device while producing images that can be accurately analyzed by a computer vision application. The techniques disclosed herein can be implemented in various electronic devices capable of capturing and processing image data, such as, for example, smart phones, wearable computers, laptops, tablets, and other mobile computing or imaging systems. In an embodiment, the techniques disclosed herein are implemented in a system-on-chip device.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: April 11, 2017
    Assignee: INTEL Corporation
    Inventors: Jorge E. Caviedes, Sin Lin Wu, Artem Zinevich, Frank Ghenassia, Dmitri Bitouk
  • Patent number: 9613294
    Abstract: A processor computes a measure of input image structural complexity of an input image, and searches a database of true positives to find one or more entries in the database that represent true positive images that are structurally similar to the input image. The processor compares a measure of signal quality of the input image and a measure of signal quality of one of the true positive images, as retrieved from the database, and based on the comparison updates a control variable that configures a signal quality conditioning process that is to be performed on the input image prior to processing of the input image by a computer vision processor thus improving performance of the computer vision task. Other embodiments are also described and claimed.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Sin Lin Wu
  • Patent number: 9609319
    Abstract: Systems and methods may provide for the detection, location, and processing of static pixels during video processing. In one example, the method may include determining if a color component value of a pixel located at a pixel location remains constant between a first frame and a next frame, determining if the pixel is a low-difference pixel, calculating a motion-compensation error of the color component, determining if the motion compensation error of the color component is large, and generating a map of static pixels including the pixel.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Nilesh Ahuja, Jorge E. Caviedes
  • Patent number: 9560382
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20170013282
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula