Patents by Inventor Jorge E Caviedes

Jorge E Caviedes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160353058
    Abstract: Three-dimensional video is presented on a two-dimensional display. The view of the video is driven by user interaction. In one example, a two-dimensional (2D) video sequence in real time with a first view is synthesized from a video image sequence with depth captured by a first device. The 2D video sequence with the first view is provided to a second device in real time. A command is received from the second device to change a view of the 2D video sequence as the video sequence is rendered. The view of the 2D video sequence is changed as it is rendered to a 2D video sequence with a second view, and the 2D video sequence with the second view is provided to the second device in real time.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 1, 2016
    Applicant: INTEL CORPORATION
    Inventors: JORGE E. CAVIEDES, SIN LIN WU
  • Publication number: 20160275369
    Abstract: A processor computes a measure of input image structural complexity of an input image, and searches a database of true positives to find one or more entries in the database that represent true positive images that are structurally similar to the input image. The processor compares a measure of signal quality of the input image and a measure of signal quality of one of the true positive images, as retrieved from the database, and based on the comparison updates a control variable that configures a signal quality conditioning process that is to be performed on the input image prior to processing of the input image by a computer vision processor thus improving performance of the computer vision task. Other embodiments are also described and claimed.
    Type: Application
    Filed: March 19, 2015
    Publication date: September 22, 2016
    Inventors: Jorge E. Caviedes, Sin Lin Wu
  • Publication number: 20160173752
    Abstract: Techniques are disclosed to adaptively control an image sensor and image signal processor (ISP), collectively known as an image pipeline, such that a minimum amount of power is consumed by an electronic device while producing images that can be accurately analyzed by a computer vision application. The techniques disclosed herein can be implemented in various electronic devices capable of capturing and processing image data, such as, for example, smart phones, wearable computers, laptops, tablets, and other mobile computing or imaging systems. In an embodiment, the techniques disclosed herein are implemented in a system-on-chip device.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 16, 2016
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Sin Lin Wu, Artem Zinevich, Frank Ghenassia, Dmitri Bitouk
  • Patent number: 9369735
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: June 14, 2016
    Assignee: Intel Corporation
    Inventors: Jorge E Caviedes, Mahesh Subedar, Khasim S Dudekula
  • Publication number: 20150235348
    Abstract: In some embodiments, color and contrast enhancement video processing may be done in one shot instead of adjusting one of color and contrast enhancement, then the other, and then going back to the first one to readjust because of the second adjustment. In some embodiments, global lightness adjustment, local contrast enhancement, and saturation enhancement may be done at the same time and in parallel. Lightness adjustment improves visibility of details for generally dark or generally light images without changing intended lighting conditions in the original shot, and is used to enhance the range of color/saturation enhancement. Local contrast enhancement done in parallel improves visual definition of objects and textures and thus local contrast and perceived sharpness.
    Type: Application
    Filed: May 5, 2015
    Publication date: August 20, 2015
    Inventors: Abhijit Sarkar, Jorge E. Caviedes, Mahesh Subedar
  • Patent number: 9053523
    Abstract: In some embodiments, color and contrast enhancement video processing may be done in one shot instead of adjusting one of color and contrast enhancement, then the other, and then going back to the first one to readjust because of the second adjustment. In some embodiments, global lightness adjustment, local contrast enhancement, and saturation enhancement may be done at the same time and in parallel. Lightness adjustment improves visibility of details for generally dark or generally light images without changing intended lighting conditions in the original shot, and is used to enhance the range of color/saturation enhancement. Local contrast enhancement done in parallel improves visual definition of objects and textures and thus local contrast and perceived sharpness.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: June 9, 2015
    Assignee: Intel Corporation
    Inventors: Abhijit Sarkar, Jorge E. Caviedes, Mahesh Subedar
  • Patent number: 9020046
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: April 28, 2015
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20150092863
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: December 8, 2014
    Publication date: April 2, 2015
    Applicant: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh Subedar, Khasim S. Kudekula
  • Publication number: 20150092866
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: December 8, 2014
    Publication date: April 2, 2015
    Applicant: INTEL CORPORATION
    Inventors: Jorge E. Caviedes, Mahesh Subedar, Khasim S. Kudekula
  • Patent number: 8994882
    Abstract: Systems and methods may provide for conducting a real-time perceptual quality analysis of a video, wherein the perceptual quality analysis includes at least one of a noise measurement, a contrast measurement and a sharpness measurement. One or more strength parameters of one or more post-processing modules in a video processing pipe may be set based on the perceptual quality analysis resulting in overall video processing that adapts to the changing perceptual quality of the input. In one example, the strength parameters include at least one of a contrast parameter and a de-noising parameter. The invention results in visually enhanced video at the output of the post-processing module.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: March 31, 2015
    Assignee: Intel Corporation
    Inventors: Kalpana Seshadrinathan, Jorge E. Caviedes
  • Patent number: 8891906
    Abstract: Methods and apparatuses use a pixel-adaptive interpolation algorithm to provide image upscaling. For each pixel location, the algorithm determines whether to use a high quality scaler algorithm (such as a polyphase filter, for example) or a directional interpolator to determine the pixel value. The determination of the appropriate interpolation algorithm is based on whether the pixel is determined to be an edge. If the pixel is determined to be an edge, the pixel-adaptive interpolation algorithm may use the directional interpolator to process the pixel; otherwise, the pixel is processed using a scaler algorithm.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: November 18, 2014
    Assignee: Intel Corporation
    Inventors: Ibrahima Ndiour, Jorge E. Caviedes
  • Patent number: 8724022
    Abstract: Frame rate conversion may be implemented using motion estimation results. Specifically, as part of the motion estimation, pixels may be labeled based on the number of matching pixels in subsequent frames. For example, pixels may be labeled as to whether they have no matching pixels, one matching pixels, or multiple matching pixels. The motion estimation and pixel labeling may then be used to interpolate pixels for frame rate conversion.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: May 13, 2014
    Assignee: Intel Corporation
    Inventors: Mahesh Subedar, Jorge E. Caviedes
  • Publication number: 20140050268
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Application
    Filed: August 6, 2013
    Publication date: February 20, 2014
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar, Khasim S. Dudekula
  • Publication number: 20140044352
    Abstract: In some embodiments, color and contrast enhancement video processing may be done in one shot instead of adjusting one of color and contrast enhancement, then the other, and then going back to the first one to readjust because of the second adjustment. In some embodiments, global lightness adjustment, local contrast enhancement, and saturation enhancement may be done at the same time and in parallel. Lightness adjustment improves visibility of details for generally dark or generally light images without changing intended lighting conditions in the original shot, and is used to enhance the range of color/saturation enhancement. Local contrast enhancement done in parallel improves visual definition of objects and textures and thus local contrast and perceived sharpness.
    Type: Application
    Filed: June 21, 2013
    Publication date: February 13, 2014
    Inventors: Abhijit Sarkar, Jorge E. Caviedes, Mahesh Subedar
  • Publication number: 20140010302
    Abstract: Systems and methods may provide for the detection, location, and processing of static pixels during video processing. In one example, the method may include determining if a color component value of a pixel located at a pixel location remains constant between a first frame and a next frame, determining if the pixel is a low-difference pixel, calculating a motion-compensation error of the color component, determining if the motion compensation error of the color component is large, and generating a map of static pixels including the pixel.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 9, 2014
    Inventors: Nilesh Ahuja, Jorge E. Caviedes
  • Publication number: 20140010478
    Abstract: Methods and apparatuses use a pixel-adaptive interpolation algorithm to provide image upscaling. For each pixel location, the algorithm determines whether to use a high quality scaler algorithm (such as a polyphase filter, for example) or a directional interpolator to determine the pixel value. The determination of the appropriate interpolation algorithm is based on whether the pixel is determined to be an edge. If the pixel is determined to be an edge, the pixel-adaptive interpolation algorithm may use the directional interpolator to process the pixel; otherwise, the pixel is processed using a scaler algorithm.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 9, 2014
    Inventors: Ibrahima Ndiour, Jorge E. Caviedes
  • Publication number: 20140002745
    Abstract: Systems and methods may provide for conducting a real-time perceptual quality analysis of a video, wherein the perceptual quality analysis includes at least one of a noise measurement, a contrast measurement and a sharpness measurement. One or more strength parameters of one or more post-processing modules in a video processing pipe may be set based on the perceptual quality analysis resulting in overall video processing that adapts to the changing perceptual quality of the input. In one example, the strength parameters include at least one of a contrast parameter and a de-noising parameter. The invention results in visually enhanced video at the output of the post-processing module.
    Type: Application
    Filed: December 9, 2011
    Publication date: January 2, 2014
    Inventors: Kalpana Seshadrinathan, Jorge E. Caviedes
  • Patent number: 8542751
    Abstract: Techniques are described that can be used to identify blocking artifacts in both vertical and horizontal directions. For blocking artifacts in a vertical direction, a horizontal gradient is determined for a pixel. Gradient smoothing is performed for pixels in the row of the pixel. A ratio of the horizontal gradient over the gradient smoothing is determined. Any pixel with a ratio above a threshold and in a segment with a length that exceeds a threshold length as potentially having block artifacts. Each column with pixels that potentially have block artifacts is inspected to determine whether a number of block artifacts in the column are a local maximum and whether there is a sufficient number of blocking artifacts in the column. Columns that satisfy both conditions are considered to include blocking artifacts.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: September 24, 2013
    Assignee: Intel Corporation
    Inventors: Nilesh A. Ahuja, Jorge E. Caviedes
  • Patent number: 8520739
    Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mehesh M. Subedar, Khasim S. Dudekula
  • Patent number: 8482670
    Abstract: Gradient analysis may be utilized to determine frame and field repeat patterns in input video data. Those frame and field repeat patterns may then be analyzed to match them with characteristic patterns associated with telecine 3:2 and 2:2 pulldown video data, for example. In addition, a progressive detector may use combing analysis to determine whether or not a particular field is progressive or interlaced data. Then, this information, together with a field flag which indicates whether field or frame analysis is appropriate, may be utilized to distinguish telecine 2:2 or 3:2 pulldowns and interlaced and progressive data in some embodiments.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: July 9, 2013
    Assignee: Intel Corporation
    Inventors: Jorge E. Caviedes, Mahesh M. Subedar