Patents by Inventor Jorge Lopez

Jorge Lopez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220208692
    Abstract: A packaged electronic device includes a semiconductor die, a conductive plate coupled to a lead, a solder structure and a package structure. The semiconductor die has opposite first and second sides and a terminal exposed along the second side. The conductive plate has opposite first and second sides and an indent that extends into the first side, the conductive plate, and the solder structure extends between the second side of the semiconductor die and the first side of the conductive plate to electrically couple the conductive plate to the terminal, and the solder structure extends into the indent. The package structure encloses the semiconductor die, the conductive plate and a portion of the lead.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Applicant: Texas Instruments Incorporated
    Inventors: Tianyi Luo, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Osvaldo Jorge Lopez, Lance Cole Wright
  • Publication number: 20220210911
    Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.
    Type: Application
    Filed: March 31, 2021
    Publication date: June 30, 2022
    Inventors: Tianyi Luo, Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Bernardo Gallegos
  • Publication number: 20220183913
    Abstract: A surgical patient interface including a base; a platform coupled to the base and including a first end and a second end, the platform configured to transition between a first position and a second position about a pivotable axis stationary relative to the base; a first abutment and a second abutment each adjustably coupled to the platform. In the first position, the platform extends between the first end and the second end in a substantially horizontal direction relative to the base, and the first abutment and the second abutment are separated by a first distance along the substantially horizontal direction. In the second position, the platform extends between the first end and the second end in a substantially vertical direction such that a torso of a patient extends in the substantially vertical direction, and the first abutment and the second abutment are separated by a second, different distance along the substantially vertical direction.
    Type: Application
    Filed: March 8, 2022
    Publication date: June 16, 2022
    Inventors: Jeffrey Schwardt, Michael Wentz, Jorge Lopez Camacho, Frank Phillips, Dennis Crandall, Alexander Vaccaro
  • Publication number: 20220181241
    Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.
    Type: Application
    Filed: May 28, 2021
    Publication date: June 9, 2022
    Inventors: Jonathan Almeria NOQUIL, Makarand Ramkrishna KULKARNI, Osvaldo Jorge LOPEZ, Yiqi TANG, Rajen Manicon MURUGAN, Liang WAN
  • Patent number: 11328105
    Abstract: Computer implemented method, system and computer program product for simulating the behavior of a knitted fabric at yarn level. The method comprises: retrieving structural information of a knitted fabric; representing each stitch with four contact nodes (4) at the end of the two stitch contacts (5) between pair of loops (2), each contact node (4) being described by a 3D position coordinate (x) and two sliding coordinates (u, v) representing the arc lengths of the two yarns in contact; measuring forces on each contact node (4) based on a force model including wrapping forces to capture the interaction of yarns at stitches; calculating the movement of each contact node (4) at a plurality of time steps using equations of motion derived using the Lagrange-Euler equations, and numerically integrated over time, wherein the equations of motion account for the mass density distributed uniformly along yarns, as well as the measured forces and boundary conditions.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: May 10, 2022
    Assignee: SEDDI, INC.
    Inventors: Gabriel Cirio, Miguel Angel Otaduy Tristan, Jorge Lopez Moreno
  • Publication number: 20220115308
    Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.
    Type: Application
    Filed: November 3, 2021
    Publication date: April 14, 2022
    Inventors: Jonathan Almeria Noquil, Satyendra Singh Chauhan, Lance Cole Wright, Osvaldo Jorge Lopez
  • Patent number: 11278462
    Abstract: A surgical patient interface including a patient support platform having a first end and a second end and configured for secure placement with respect to at least one surface of a building structure, wherein the patient support platform is configured to interface with a patient such that at least the torso of the patient extends in a generally vertical direction between the first end and the second end of the patient support platform, and one or more patient supports coupled to the patient support platform and configured to secure the patient to the patient support platform, such that the at least the torso of the patient is held in a substantially static condition, and such that a target portion of the patient's skin is accessible for surgical puncture or incision.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 22, 2022
    Assignee: NuVasive Specialized Orthopedics, Inc.
    Inventors: Jeffrey Schwardt, Michael Wentz, Jorge Lopez Camacho, Frank Phillips, Dennis Crandall, Alexander Vaccaro
  • Publication number: 20220071670
    Abstract: The present disclosure broadly provides applications of communication at ultrasound frequencies to establish transcutaneous data communication between medical devices located on and/or within a body of a patient, including inter alia: features for adjustable implants including data communication, hermetic containment, and torque amplification features.
    Type: Application
    Filed: August 18, 2021
    Publication date: March 10, 2022
    Inventors: Shanbao Cheng, Jorge Lopez Camacho, Youngsam Bae, Michael Moeller, Gabriel Buenviaje, Shawn Placie
  • Patent number: 11250187
    Abstract: Computer implemented method, system and computer program product for simulating the behavior of a woven fabric at yarn level. The method comprises. retrieving the layout of warp yarns (1), weft yarns (2) and yarn crossing nodes (3): describing each yarn crossing node (3) by a 3D position coordinate (x) and two sliding coordinates, warp sliding coordinate (u) and weft sliding coordinate (v) representing the sliding of warp (1) and weft (2) yarns; measuring forces on each yarn crossing node (3) based on a force model, the forces being measured on both the 3D position coordinate (x) and the sliding coordinates (u, v); calculating the movement of each yarn crossing node (3) using equations of motion derived using the Lagrange-Euler equations, and numerically integrated over time, wherein the equations of motion account for the mass density distributed uniformly along yarns, as well as the measured forces and boundary conditions.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: February 15, 2022
    Assignee: SEDDI, INC.
    Inventors: Gabriel Cirio, Miguel Angel Otaduy Tristan, David Miraut Andres, Jorge Lopez Moreno
  • Publication number: 20220015811
    Abstract: The present disclosure broadly provides applications of communication at ultrasound frequencies to establish transcutaneous data communication between medical devices located on and/or within a body of a patient, including inter alia: features for adjustable implants including data communication, hermetic containment, and torque amplification features.
    Type: Application
    Filed: June 29, 2021
    Publication date: January 20, 2022
    Inventors: Jorge Lopez Camacho, Shanbao Cheng, Youngsam Bae, Shawn Placie, Michael Moeller
  • Publication number: 20210356407
    Abstract: According to various embodiments of the present invention, an optical capture system is provided. In one embodiment, a micro-scale optical capturing system is provided with low divergence (approximately 1°) of the incident light and low acceptance angle (<8°) of the captured light. According to embodiments, a micro-scale optical capturing system is provided with a large number of collimated high-power white LEDs as light sources, between 60 and 100 units, for example, and may be positioned at distances of about 650 mm from the sample. In one embodiment, a digital camera using 50 mm focal objective with a 25 mm length extension tube captures images of the sample. This provides a working distance of approximately 100 mm and at the same time maintains ×0.5 magnification for microscale captures, with an image size of 4×4 microns per pixel.
    Type: Application
    Filed: July 30, 2021
    Publication date: November 18, 2021
    Applicant: SEDDI, INC.
    Inventors: Carlos ALIAGA, Raúl ALCAIN, Carlos HERAS, Iñigo SALINAS, Sergio SUJA, Elena GARCÉS, Jorge LÓPEZ
  • Patent number: 11177197
    Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 16, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan Almeria Noquil, Satyendra Singh Chauhan, Lance Cole Wright, Osvaldo Jorge Lopez
  • Patent number: 11177246
    Abstract: A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Osvaldo Jorge Lopez, Walter Hans Paul Schroen, Jonathan Almeria Noquil, Thomas Eugene Grebs, Simon John Molloy
  • Publication number: 20210265246
    Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.
    Type: Application
    Filed: May 12, 2021
    Publication date: August 26, 2021
    Inventors: Tianyi Luo, Jonathan Almeria Noquil, Osvaldo Jorge Lopez
  • Publication number: 20210256172
    Abstract: The technology relates to modeling cross-sections of yarn. For instance, modeling cross-sections of yarn may include receiving yarn simulation input comprising a descriptive model of a general curvature followed by the yarn, providing a plurality of fibers distributed raidally from the center of a ply, setting a base position based on parameters, applying a strain model to simulate the effect of stretch forces applied to the yarn, and outputting a yarn model indicating position and directionality of fibers in the yarn. The technology also relates to real-time modeling of a garment comprising a fabric. For instance, real-time modeling of a garment may include providing an input associated with one or more parameters of the fabric, receiving frames of a computer simulated garment, the computer simulated garment including a simulation of the fabric, the fabric simulation including yarns simulated based on a yarn model.
    Type: Application
    Filed: May 4, 2021
    Publication date: August 19, 2021
    Applicant: SEDDI, INC.
    Inventors: Carlos CASTILLO, Miguel A. OTADUY, Carlos ALIAGA, Jorge LOPEZ
  • Patent number: 11043477
    Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 22, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan Almeria Noquil, Osvaldo Jorge Lopez, Haian Lin
  • Patent number: 11024564
    Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: June 1, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tianyi Luo, Jonathan Almeria Noquil, Osvaldo Jorge Lopez
  • Publication number: 20210090980
    Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Inventors: Jonathan Almeria Noquil, Satyendra Singh Chauhan, Lance Cole Wright, Osvaldo Jorge Lopez
  • Patent number: 10930582
    Abstract: Disclosed embodiments relate to a semiconductor device. A semiconductor device is fabricated by attachment of a first chip to a first surface of a pad of a leadframe. Each of one or more terminals of the first chip is connected to a respective lead of the leadframe. The first chip and the first surface of the pad are then encapsulated in a packaging material, while leaving an opposite second surface of the pad exposed. A second chip is attached to a recessed portion of the second surface of the pad so that at least one terminal of the second chip is substantially coplanar with an un-recessed portion of the second surface. In one embodiment, a third chip is also attached to the recessed portion of the second surface so that at least one terminal of the third chip is substantially coplanar with the un-recessed portion of the second surface.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: February 23, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil
  • Publication number: 20200410146
    Abstract: Computer implemented method, system and computer program product for simulating the behavior of a knitted fabric at yarn level. The method comprises: retrieving structural information of a knitted fabric; representing each stitch with four contact nodes (4) at the end of the two stitch contacts (5) between pair of loops (2), each contact node (4) being described by a 3D position coordinate (x) and two sliding coordinates (u, v) representing the arc lengths of the two yarns in contact; measuring forces on each contact node (4) based on a force model including wrapping forces to capture the interaction of yarns at stitches; calculating the movement of each contact node (4) at a plurality of time steps using equations of motion derived using the Lagrange-Euler equations, and numerically integrated over time, wherein the equations of motion account for the mass density distributed uniformly along yarns, as well as the measured forces and boundary conditions.
    Type: Application
    Filed: September 15, 2020
    Publication date: December 31, 2020
    Applicant: SEDDI, INC.
    Inventors: Gabriel CIRIO, Miguel Angel OTADUY TRISTAN, Jorge LOPEZ MORENO