Patents by Inventor Jorge P. Rodriguez

Jorge P. Rodriguez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10468730
    Abstract: Various embodiments may be generally directed to techniques for using an observed battery stress history to manage operation of a computing system component in a high power performance mode when powered by a battery. Various embodiments include techniques for tracking stresses to a battery. Various embodiments include techniques for comparing the battery stress history to a degradation baseline for the battery. Various embodiments include techniques for developing a degradation baseline for a battery including, for example, a degradation baseline based on expected stress to a battery and/or a degradation baseline based on a battery reliability model. Various embodiments include techniques for determining a battery stress surplus or deficit. Various embodiments include techniques for managing operation of a performance enhancing mode or high power performance mode of a computing system component based on the determined battery stress surplus or deficit.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: November 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Jorge P. Rodriguez, Alexander B. Uan-Zo-Li, Naoki Matsumura, Andrew Keates, James G. Hermerding, II
  • Publication number: 20190210334
    Abstract: Embodiments disclosed herein include multilayer cast films having a first outer layer, a core layer, and a second outer layer, wherein the first outer layer comprises (a) a linear low density polyethylene (LLDPE), ultra-low density polyethylene (ULDPE), a first polyethylene composition, or combinations of two or more thereof, and (b) polyisobutylene, and the core layer comprises a core layer polyethylene composition.
    Type: Application
    Filed: August 30, 2017
    Publication date: July 11, 2019
    Inventors: Marlos Giuntini De Oliveira, Teresa P. Karjala, Mustafa Bilgen, Jorge Caminero Gomes, Maximiliano Zanetti, Miguel A. Molano Niampira, Jorge Mario Rodriguez Camelo, Camila Do Valle, Guillermo A. Raimondi
  • Patent number: 10234920
    Abstract: In one embodiment, a processor includes: at least one core to execute instructions; a power controller to control power consumption of the processor; and a storage to store a plurality of entries to associate a dynamic capacitance with a time duration for which a current spike is to be exposed to a power delivery component. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Jorge P. Rodriguez
  • Patent number: 10222851
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • Publication number: 20190041951
    Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.
    Type: Application
    Filed: June 19, 2018
    Publication date: February 7, 2019
    Inventors: Dorit Shapira, Anand K. Enamandram, Daniel Cartagena, Krishnakanth Sistla, Jorge P. Rodriguez, Efraim Rotem, Nir Rosenzweig
  • Publication number: 20180059757
    Abstract: In one embodiment, a processor includes: at least one core to execute instructions; a power controller to control power consumption of the processor; and a storage to store a plurality of entries to associate a dynamic capacitance with a time duration for which a current spike is to be exposed to a power delivery component. Other embodiments are described and claimed.
    Type: Application
    Filed: August 31, 2016
    Publication date: March 1, 2018
    Inventors: Avinash N. Ananthakrishnan, Jorge P. Rodriguez
  • Publication number: 20170351322
    Abstract: An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage signal, compare a first voltage level of the unfiltered input voltage signal to a first reference voltage level, and generate a control signal operative to lower operation power of one or more of the one or more platform components when the first voltage level is less than the first reference voltage level.
    Type: Application
    Filed: January 9, 2017
    Publication date: December 7, 2017
    Applicant: INTEL CORPORATION
    Inventors: ALEXANDER B. UAN-ZO-LI, JORGE P. RODRIGUEZ, PHILIP R. LEHWALDER, PATRICK K. LEUNG, JAMES G. HERMERDING, II, VASUDEVAN SRINIVASAN
  • Patent number: 9612643
    Abstract: Methods and apparatus relating to controlling processor slew rates based on battery charge state/level are described. In one embodiment, logic causes modification to a slew rate of a processor based on at least a charge level of a battery pack. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 29, 2014
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Alexander B. Uan-Zo-Li, Don J. Nguyen, Gang Ji, Philip R. Lehwalder, Jorge P. Rodriguez, Vasudevan Srinivasan
  • Publication number: 20170092996
    Abstract: Various embodiments may be generally directed to techniques for using an observed battery stress history to manage operation of a computing system component in a high power performance mode when powered by a battery. Various embodiments include techniques for tracking stresses to a battery. Various embodiments include techniques for comparing the battery stress history to a degradation baseline for the battery. Various embodiments include techniques for developing a degradation baseline for a battery including, for example, a degradation baseline based on expected stress to a battery and/or a degradation baseline based on a battery reliability model. Various embodiments include techniques for determining a battery stress surplus or deficit. Various embodiments include techniques for managing operation of a performance enhancing mode or high power performance mode of a computing system component based on the determined battery stress surplus or deficit.
    Type: Application
    Filed: September 26, 2015
    Publication date: March 30, 2017
    Applicant: Intel Corporation
    Inventors: JORGE P. RODRIGUEZ, ALEXANDER B. UAN-ZO-LI, NAOKI MATSUMURA, ANDY KEATES, JAMES G. HERMERDING, II
  • Publication number: 20170038815
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 9, 2017
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • Patent number: 9541991
    Abstract: An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage signal, compare a first voltage level of the unfiltered input voltage signal to a first reference voltage level, and generate a control signal operative to lower operation power of one or more of the one or more platform components when the first voltage level is less than the first reference voltage level.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: January 10, 2017
    Assignee: INTEL CORPORATION
    Inventors: Alexander B. Uan-Zo-Li, Jorge P. Rodriguez, Philip R. Lehwalder, Patrick K. Leung, James G. Hermerding, II, Vasudevan Srinivasan
  • Patent number: 9477243
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • Publication number: 20160291680
    Abstract: An electronic device comprising: a power monitor to receive system power to be delivered to a processor and to one or more components of a system, the power monitor to provide information corresponding to the system power, and a processor to change a performance of the processor based at least in part on the information corresponding to the system power.
    Type: Application
    Filed: December 27, 2013
    Publication date: October 6, 2016
    Inventors: Ruoying Mary MA, James G. HERMERDING II, Efraim ROTEM, Jorge P. RODRIGUEZ, Jeffrey A. CARLSON
  • Patent number: 9411398
    Abstract: An electronic apparatus is provided that includes a processor, a voltage regulator, a battery controller and an embedded controller. The voltage regulator to receive an input voltage and to provide an output voltage to the processor. The battery controller to store electronic device information and to receive battery information related to a current battery power. The embedded controller to receive the electronic device information and the battery information from the battery controller, and the embedded controller to provide power information to the processor based on the received information.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: August 9, 2016
    Assignee: INTEL CORPORATION
    Inventors: Gang Ji, Alexander B. Uan-Zo-Li, Jorge P. Rodriguez, Andy Keates, Vasudevan Srinivasan
  • Publication number: 20160226283
    Abstract: An electronic device and method may change a default current limit of a USB power system. The electronic system may include a cable detector component to detect a plug to couple to a port, a source detector component to determine an identification of a power source, and circuitry to change an input current limit or an output current limit of the electronic device.
    Type: Application
    Filed: September 24, 2014
    Publication date: August 4, 2016
    Inventors: Chee Lim NGE, Jorge P. RODRIGUEZ
  • Patent number: 9395774
    Abstract: Methods and apparatus relating to total platform power control are described. In one embodiment, power consumption by one or more processor cores of a processor and one or more components coupled to the processor are modified based on a total platform power consumption value. The platform, in turn, includes the processor and the one or more components. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, James G. Hermerding, II, Ruoying Ma, Jorge P. Rodriguez, Nir Rosenzweig
  • Publication number: 20160179110
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 23, 2016
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • Patent number: 9337661
    Abstract: An apparatus including a storage area to store instructions and a controller to control power in a first device based on the instructions. In operation, the controller generates one or more signals to combine power from a first power source and a second power source for a hybrid power operation. The controller is to generate the one or more signals based on a connection state of the first device, multiple connection states of the first device, a charge level of a battery of the first device, or a combination thereof.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 10, 2016
    Assignee: Intel Corporation
    Inventors: Matthew Coakley, Alexander B. Uan-Zo-Li, Jorge P. Rodriguez, Basavaraj B. Astekar, Gary L. Bookhardt
  • Publication number: 20150277535
    Abstract: Methods and apparatus relating to controlling processor slew rates based on battery charge state/level are described. In one embodiment, logic causes modification to a slew rate of a processor based on at least a charge level of a battery pack. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 29, 2014
    Publication date: October 1, 2015
    Applicant: Intel Corporation
    Inventors: ALEXANDER B. UAN-ZO-LI, DON J. NGUYEN, GANG JI, PHILIP R. LEHWALDER, JORGE P. RODRIGUEZ, VASUDEVAN SRINIVASAN
  • Publication number: 20140336963
    Abstract: Systems and methods of enabling a battery system to intelligently provide its current support capability include logic to determine current battery power status information. The current battery power status information may be compared with a set of programmed battery power status information to determine a match. There may be logic to indicate the current battery power status information based on the match.
    Type: Application
    Filed: March 30, 2012
    Publication date: November 13, 2014
    Inventors: Gang Ji, Alexander B. Uan-Zo-li, Mazen G. Gedeon, Jorge P. Rodriguez, Basavaraj B. Astekar