Abstract: Methods and apparatus relating to controlling processor slew rates based on battery charge state/level are described. In one embodiment, logic causes modification to a slew rate of a processor based on at least a charge level of a battery pack. Other embodiments are also disclosed and claimed.

Abstract: Systems and methods of enabling a battery system to intelligently provide its current support capability include logic to determine current battery power status information. The current battery power status information may be compared with a set of programmed battery power status information to determine a match. There may be logic to indicate the current battery power status information based on the match.

Abstract: Methods and apparatus relating to controlling power consumption by a Power Supply Unit (PSU) during idle state are described. In one embodiment, a power supply unit enters a lower power consumption state (e.g. S9) based on power state information, corresponding to one or more components of the platform, and comparison of a first value (corresponding to a frequency/frequentness of entry into the lower power consumption state) to a first threshold value. Other embodiments are also disclosed and claimed.

Abstract: Systems and methods of managing platform power consumption may involve determining a power consumption level of a platform based on at least in part a current supplied by an AC adaptor. A power limit of an integrated circuit in the platform can be determined based on at least in part the power consumption level of the platform, wherein the power level may be applied to the integrated circuit.

Abstract: Methods and apparatus relating to total platform power control are described. In one embodiment, power consumption by one or more processor cores of a processor and one or more components coupled to the processor are modified based on a total platform power consumption value. The platform, in turn, includes the processor and the one or more components. Other embodiments are also disclosed and claimed.

Abstract: An apparatus including a storage area to store instructions and a controller to control power in a first device based on the instructions. In operation, the controller generates one or more signals to combine power from a first power source and a second power source for a hybrid power operation. The controller is to generate the one or more signals based on a connection state of the first device, multiple connection states of the first device, a charge level of a battery of the first device, or a combination thereof.

Abstract: An electronic device may include a power delivery system to provide a voltage, and an integrated circuit having a processor to receive the voltage. When the received voltage exceeds a prescribed value, the integrated circuit to perform an act to consume current from the power delivery system.

Abstract: An apparatus may comprise a platform power protection circuit to monitor an electric current over a platform input line, the electric current received on the platform input line from a current source, and output an alert signal from a comparator when current output is determined to exceed a current threshold. The apparatus may further include logic to assert a control signal to reduce power consumption in one or more platform components coupled to the platform input line when the alert signal is received. Other embodiments are disclosed and claimed.

Abstract: An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage signal, compare a first voltage level of the unfiltered input voltage signal to a first reference voltage level, and generate a control signal operative to lower operation power of one or more of the one or more platform components when the first voltage level is less than the first reference voltage level.

Abstract: An electronic apparatus is provided that includes a processor, a voltage regulator, a battery controller and an embedded controller. The voltage regulator to receive an input voltage and to provide an output voltage to the processor. The battery controller to store electronic device information and to receive battery information related to a current battery power. The embedded controller to receive the electronic device information and the battery information from the battery controller, and the embedded controller to provide power information to the processor based on the received information.

Abstract: Systems and methods of managing platform power consumption may involve determining a power consumption level of a platform based on at least in part a current supplied by an AC adaptor. A power limit of an integrated circuit in the platform can be determined based on at least in part the power consumption level of the platform, wherein the power level may be applied to the integrated circuit.

Abstract: An audio noise mitigation approach. For one aspect, a first voltage associated with a first power management state is provided. A signal responsive to an indication associated with at least a first type of periodic exit event is received and responsive to the signal, a transition to a second voltage associated with a second state is initiated, a rate of the transition to the second voltage being slower than a similar voltage transition initiated in response to a non-periodic exit event.

Abstract: An integrated circuit device, such as a processor initiates a transition to a first power management state. The device then receives a request to exit the first power management state and, in response exits the first power management state at the highest of a reference operating voltage, such as a minimum operating voltage, and a current voltage. For one aspect, an analog to digital converter may be used to determine the current voltage level. Further, for one aspect the first power management state may be a deeper sleep (C4) state, and the processor may quickly exit to a C2 state in response to a bus event such as a bus snoop.

Abstract: A multilayer capacitor is constructed to minimize equivalent series inductance (ESL) and to achieve large capacitance. The capacitor includes first and second main go surface terminal electrodes provided on a first main surface of the main body of the multilayer capacitor. First and second side surface terminal electrodes are disposed on four side surfaces of the main body. The main body is divided into a low ESL section of the first main-surface side and a high capacitance section of the second main-surface side. In the low ESL section, in addition to first and second low ESL internal electrodes, a first conductive via-hole electrically connecting the first low ESL internal electrode to the first main surface terminal electrode and a second conductive via-hole electrically connecting the second low ESL internal electrode to the second main surface terminal electrode are provided.