Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

Abstract: A method and system are disclosed for calibrating a mid-voltage node in an integrated circuit including an input-output circuit having charge-recycling stacked voltage domains including at least first and second voltage domains. In one embodiment, the method comprises transmitting data through the input-output circuit, including transmitting a first portion of the data across the first voltage domain, and transmitting a second portion of the data across the second voltage domain. The method further comprises measuring a specified characteristic of the data transmitted through the input-output circuit; and based on the measured specified characteristic, adjusting a voltage of said mid-voltage node to a defined value. The voltage of the mid-voltage node may be adjusted to accomplish a number of objectives, for example, to achieve a desired trade-off between power and performance, or so that the two voltage domains have the same performance.

Abstract: There is provided a tank based oscillator. The oscillator includes one or more active devices, one or more passive devices, and a tank circuit decoupled from the active devices using at least one of the one or more passive devices. A coupling ratio between the tank circuit and the one or more active devices is set such that a maximum value of an oscillation amplitude of the tank circuit is limited based upon a breakdown of only the one or more passive devices.

Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.

Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.

Abstract: A method and system are disclosed for calibrating a mid-voltage node in an integrated circuit including an input-output circuit having charge-recycling stacked voltage domains including at least first and second voltage domains. In one embodiment, the method comprises transmitting data through the input-output circuit, including transmitting a first portion of the data across the first voltage domain, and transmitting a second portion of the data across the second voltage domain. The method further comprises measuring a specified characteristic of the data transmitted through the input-output circuit; and based on the measured specified characteristic, adjusting a voltage of said mid-voltage node to a defined value. The voltage of the mid-voltage node may be adjusted to accomplish a number of objectives, for example, to achieve a desired trade-off between power and performance, or so that the two voltage domains have the same performance.

Abstract: Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

Abstract: Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

Abstract: Equalization techniques for compensating distortion associated with a communications channel are provided. In one aspect of the invention, a method/apparatus for equalizing an input signal received from a communications channel includes the following steps/operations. At least one sampling is generated from the received input signal based on a clock signal unrelated to a clock signal used to recover data associated with the received input signal. Distortion associated with the communications channel is then compensated for based on at least a portion of the at least one generated sampling.

Abstract: Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

Abstract: Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

Abstract: Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tuning steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering.

Abstract: A method of forming a circuit includes forming a transimpedance amplifier having a first input node and a second input node. The method also includes forming a feedback circuit having a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal.

Abstract: A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom.

Abstract: A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter.

Abstract: A circuit includes a transimpedance amplifier portion having a first input node and a second input node, and a feedback circuit portion comprising a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal.

Abstract: A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter.

Abstract: There is provided a method for reducing lock time in a phase locked loop. The method includes detecting a saturation condition on a path within the phase locked loop. The method further includes temporarily applying saturation compensation along the path when the saturation condition is detected.

Abstract: A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter.

Abstract: Phase profile generator systems and methods are disclosed. A system includes a signal generator, a target phase trajectory module, an error detector and a control loop filter. The signal generator is configured to generate an output signal. In addition, the target phase trajectory module is configured to track a target phase trajectory and determine a next adjustment of the output signal to conform the output signal to a portion of the target phase trajectory. Further, the error detector is configured to determine an error between the output signal and a current target phase trajectory value that precedes the portion of the target phase trajectory, where the determination of the error is independent of the next adjustment of the output signal. Moreover, the control loop filter is configured to control the signal generator in accordance with both the next adjustment and the error to generate a phase profile.