Abstract: Circuits and methods are provided in which fine tuning control of a DCO (digitally controlled oscillator) circuit in a digital PLL circuit is realized by dither controlling a multiplexer circuit under digital control to selectively output one of a plurality of analog control voltages with varied voltage levels that are input to a fractional frequency control port of the DCO to drive tuning elements of the DCO at fractional frequency resolution and achieve continuous fine tuning of the DCO under analog control.

Abstract: Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach.

Abstract: Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach.

Abstract: Circuits and methods are provided in which fine tuning control of a DCO (digitally controlled oscillator) circuit in a digital PLL circuit is realized by dither controlling a multiplexer circuit under digital control to selectively output one of a plurality of analog control voltages with varied voltage levels that are input to a fractional frequency control port of the DCO to drive tuning elements of the DCO at fractional frequency resolution and achieve continuous fine tuning of the DCO under analog control.

Abstract: PLL (phase locked loop) circuits and methods are provided in which PWM (pulse width modulation) techniques are to achieve continuous fine tuning control of DCO (digitally controlled oscillator) circuits. In general, pulse width modulation techniques are applied to further modulate dithered control signals that are used to enhance the frequency tuning resolution of the DCO such that the dithered control signals are applied to the fractional tracking control port of the DCO for a selected fraction of a full clock signal based pulse width modulation applied.

Abstract: A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO).

Abstract: Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point.

Abstract: A control system for generating an electronic circuit clock signal that can optimize operating frequency margins by responding to short term effects by quickly varying the clock frequency and long term effects by finding an optimal frequency point. A sensor indicates frequency margins associated with safe use of the clock signal, and these frequency margins are input into a frequency compensator and used to determine whether the system is operating within acceptable margins, or alternatively to modify the operating clock frequency on a short-term basis in order to achieve acceptable operating margins. The requests for frequency adjustment by the frequency compensator are provided to a frequency filter, which combines such request with a maintained/accumulated history of previous short-term frequency requests that have previously been made in order to determine whether an update needs to be made to the target frequency to provide long-term frequency control.

Abstract: A control system for generating an electronic circuit clock signal that can optimize operating frequency margins by responding to short term effects by quickly varying the clock frequency and long term effects by finding an optimal frequency point. A sensor indicates frequency margins associated with safe use of the clock signal, and these frequency margins are input into a frequency compensator and used to determine whether the system is operating within acceptable margins, or alternatively to modify the operating clock frequency on a short-term basis in order to achieve acceptable operating margins. The requests for frequency adjustment by the frequency compensator are provided to a frequency filter, which combines such request with a maintained/accumulated history of previous short-term frequency requests that have previously been made in order to determine whether an update needs to be made to the target frequency to provide long-term frequency control.

Abstract: A data transmission system includes parallel data paths for transmitting data, and an encoder for encoding the data such that an error correction code is generated for data at a same bit position across the parallel data paths.

Abstract: A technique to mitigate noise spikes in an electronic circuit device such as an integrated circuit. The clock frequency of a clock signal used by the electronic circuit is controlled such that instantaneously large changes to the clock frequency are avoided by use of a frequency filter that is capable of generating frequency ramps having a linear slope which is used as a feedback signal in a digital phase-locked loop clock circuit in lieu of a discrete, stair-stepped feedback control signal.

Abstract: An apparatus, method, and computer program product to identify types of errors that occur in a communications device under test and where only the presence of an error is indicated by an error checker. Each presence of an error bit in an error signal during a first period of time output from the error data checker is identified. The error bit indicates only that a mismatch occurred between an input signal input into the device and an output signal output from the device. The error bit is generated in response to an error in the device under test. The error bit includes no information about a type of the error. The type of the error is determined by determining a number of occurrences of the error bit in the error signal during the first period of time.

Abstract: A system in one embodiment includes a voltage controlled oscillator; at least two varactors coupled to a tank node, each of the varactors being of a different physical size, the tank node being coupled to the voltage controlled oscillator; and switches for selectively turning the varactors on and off, wherein switching a first of the varactors from off to on and a second of the varactors from on to off creates a capacitance step of less than about 10 fF thereby tuning the voltage controlled oscillator from a first state to a second state.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: A technique is disclosed for processing a binary coded signal to generate a thermometer coded signal. Such technique includes the following steps. A binary coded input signal is obtained. A binary arithmetic operation is performed on a least significant bit (LSB) portion of the binary coded input signal. At least one signal representative of an occurrence of one of an overflow condition and an underflow condition is generated, in response to the binary arithmetic operation performed on the LSB portion. A thermometer coded signal is shifted in response to the signal representative of the occurrence of one of the overflow condition and the underflow condition, wherein shifting of the thermometer coded signal represents one of incrementing and decrementing a most significant bit (MSB) portion of the binary coded input signal. The thermometer coded signal is outputted.

Abstract: A latency locked loop (LLL) circuit for a first in first out (FIFO) buffer, includes a latency error estimator for estimating a latency error for the buffer by measuring a latency of the buffer and comparing the measured latency to a reference latency, a loop filter for converting the latency error into a computed data rate, and a data rate generator for adjusting a rate of data at least one of into and out of the buffer such that the rate of data matches the computed data rate.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point.

Abstract: Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach.