Patents by Inventor Jose A. Vargas
Jose A. Vargas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160139010Abstract: A system for processing biological specimens mounted on microscope slides by adding and removing processing fluids from microscope slides by means of capillary action using a slide holder capable of holding multiple microscope slides, and a spacer positioned in between two slides of a slide pair to create a capillary gap. A capillary gap adjuster can be used to pinch and release one end of the slide pair to create a pulsatile action to mix the reagent within the capillary gap. The system may further include a reagent holder, an absorbent pad, a series of reagent baths, and an incubator for holding one or more slide holders.Type: ApplicationFiled: November 18, 2015Publication date: May 19, 2016Inventors: Alfonso Heras, Jose Vargas, Jack Novak
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Patent number: 9342394Abstract: Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.Type: GrantFiled: December 29, 2011Date of Patent: May 17, 2016Assignee: Intel CorporationInventors: Murugasamy Nachimuthu, Mohan J. Kumar, Theodros Yigzaw, Jose A. Vargas, Rajender Kuramkote
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Patent number: 9317360Abstract: In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.Type: GrantFiled: December 29, 2011Date of Patent: April 19, 2016Assignee: Intel CorporationInventors: Jose A. Vargas, Mohan J. Kumar, James B. Crossland, Murugasamy K. Nachimuthu, Theodros Yigzaw
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Patent number: 9223738Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: GrantFiled: November 2, 2012Date of Patent: December 29, 2015Assignee: Intel CorporationInventors: Mani Ayyar, Eric Richard Delano, Ioannis Y. Schoinas, Akhilesh Kumar, Doddaballapur Jayasimha, Jose A. Vargas
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Patent number: 9150972Abstract: Disclosed is a Fuel Augmentation Support System (“FASS”). The disclosed FASS herein is useful to support a multitude of electrolysis cell composition and designs. It provides a system which supports an uncontaminated electrolysis process via the prohibition of other elements from intermingling with the electrolytic fluid, without creating excess positive or negative pressures in a FASS operations, an example of producing gas using the electrolysis of distilled water combined with a catalyst of potassium Hydroxide will be used since it is a method to generate a combustible gas used to enhance the combustion of practically any fuel. The FASS exploits an efficient utilization of electrons generated between the electrolysis electrodes in order to produce gas and achieve it's goals.Type: GrantFiled: March 26, 2013Date of Patent: October 6, 2015Inventors: Alfredo Vargas, Jose A Vargas
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Publication number: 20150095705Abstract: A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Inventors: ASHOK RAJ, MOHAN J. KUMAR, JOSE A. VARGAS, WILLIAM G. AULD, CAMERON B. MCNAIRY, THEODROS YIGZAW, JAMES B. CROSSLAND, ANTHONY E. LUCK
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Publication number: 20140298140Abstract: An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.Type: ApplicationFiled: December 22, 2011Publication date: October 2, 2014Inventors: Theodros Yigzaw, Oded Lempel, Hisham Hafi, Geeyarpuram N Santhanakrisnan, Jose A Vargas, Ganapati N Srinivasa, Mohan J Kumar, Larisa Novakovsky, Lihu Rappoport, Chen Koren, Julius Yuli Mandelblat
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Publication number: 20140237299Abstract: Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.Type: ApplicationFiled: December 29, 2011Publication date: August 21, 2014Inventors: Murugasamy Nachimuthu, Mohan J. Kumar, Theodros Yigzaw, Jose A. Vargas, Rajendra Kuramkote
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Publication number: 20140223226Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.Type: ApplicationFiled: December 22, 2011Publication date: August 7, 2014Inventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrushnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
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Patent number: 8645797Abstract: In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.Type: GrantFiled: December 12, 2011Date of Patent: February 4, 2014Assignee: Intel CorporationInventors: Theodros Yigzaw, Yen-Cheng Liu, Mohan J. Kumar, Jose A. Vargas
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Publication number: 20130339829Abstract: In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.Type: ApplicationFiled: December 29, 2011Publication date: December 19, 2013Inventors: Jose A. Vargas, Mohan J. Kumar, James B. Crossland, Murugasamy K. Nachimuthu, Theodros Yigzaw
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Publication number: 20130332781Abstract: Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.Type: ApplicationFiled: June 6, 2012Publication date: December 12, 2013Inventors: Sarathy Jayakumar, Mohan J. Kumar, Jose A. Vargas
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Publication number: 20130304957Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: ApplicationFiled: November 2, 2012Publication date: November 14, 2013Inventors: Mani Ayyar, Eric Richard Delano, Ioanns Y. Schoinas, Akhilesh Kumar, Doddaballapur Jayasimha, Jose A. Vargas
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Publication number: 20130275810Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.Type: ApplicationFiled: September 29, 2011Publication date: October 17, 2013Inventors: Theodros Yigzaw, Kai Cheng, Mohan J. Kumar, Jose A. Vargas, Gopikrishna Jandhyala
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Publication number: 20130151930Abstract: In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.Type: ApplicationFiled: December 12, 2011Publication date: June 13, 2013Inventors: Theodros Yigzaw, Yen-Cheng Liu, Mohan J. Kumar, Jose A. Vargas
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Patent number: 8327113Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: GrantFiled: September 23, 2008Date of Patent: December 4, 2012Assignee: Intel CorporationInventors: Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose A. Vargas
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Patent number: 8296768Abstract: In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.Type: GrantFiled: June 30, 2007Date of Patent: October 23, 2012Assignee: Intel CorporationInventors: Koichi Yamada, Douglas E. Covelli, Jose A. Vargas, Mohan J. Kumar
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Patent number: 8171121Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: GrantFiled: September 23, 2008Date of Patent: May 1, 2012Assignee: Intel CorporationInventors: Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose A. Vargas
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Patent number: 7734741Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: GrantFiled: December 13, 2004Date of Patent: June 8, 2010Assignee: Intel CorporationInventors: Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose A. Vargas
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Patent number: 7546487Abstract: Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.Type: GrantFiled: September 15, 2005Date of Patent: June 9, 2009Assignee: Intel CorporationInventors: Suresh Marisetty, Andrew J. Fish, Koichi Yamada, Scott D. Brenden, James B. Crossland, Shivnandan Kaushik, Mohan J. Kumar, Jose A. Vargas