Abstract: Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.

Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Abstract: In a method for switching to a spare memory module during runtime, a processing system determines that utilization of an active memory module in the processing system should be discontinued. The processing system may then activate a mirror copy mode that causes a memory controller in the processing system to copy data from the active memory module to the spare memory module when the data is accessed in the active memory module. An operating system (OS) in the processing system may then access data in the active memory module to cause the memory controller to copy data from the active memory module to the spare memory module. The processing system may then reconfigure the memory controller to direct reads and writes to the spare memory module instead of the active memory module. Other embodiments are described and claimed.

Abstract: In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.

Abstract: A method according to one embodiment may include partitioning a multi-core processor into a first partition and a second partition, the first partition including a first processor core and a first interrupt controller configured to store a first partition identifier, the second partition including a second processor core and a second interrupt controller configured to store a second partition identifier. The method may also include receiving, by the first interrupt controller and the second interrupt controller, at least one interrupt that includes a partition identifier. The method may also include comparing, by the first interrupt controller, the partition identifier included with the interrupt to the first partition identifier stored in the first interrupt controller.

Abstract: Techniques for using measurements made by UEs to improve network performance are described. In one aspect, RF parameters of cells may be determined by taking into account mobility of the UEs. Mobility information for the UEs may be determined based on measurement report messages (MRMs) sent by these UEs for handover. RF parameters such as antenna down-tilt, antenna orientation, antenna pattern, and/or pilot power of the cells may be determined based on the mobility information for the UEs. In another aspect, the RF parameters of cells may be dynamically adjusted based on loading conditions of cells. In yet another aspect, the location of a UE may be determined based on an MRM sent by the UE for handover. The MRM may include timing measurements for multiple cells. The location of the UE may be determined based on the timing measurements.

Abstract: Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.

Abstract: The invention relates to series reactor beds containing different oligomerization catalysts and having independent temperature control, and processes for the oligomerization of light olefins to heavier olefins using such series reactor beds.

Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Abstract: A method for assigning a device to a first virtual machine includes connecting the device, directly or indirectly, to a computer through an interconnect. The first virtual machine and a second virtual machine are run on the computer. The device is assigned to the first virtual machine for exclusive use by the first virtual machine, and the assignment is enforced.

Abstract: A wireless silencing device transmits a wireless silence signal in or near a region where extraneous sound is undesired. Wireless devices in receipt of the wireless silence signal may use the signal to determine whether to enable an auto silence mode of operation.

Abstract: Techniques for selectively forwarding interrupt signals to virtual machines.

Abstract: A method for accessing a configuration data space for a device connected to a processor through an interconnect includes receiving a request from the processor to access the processor's addressable space. The request is generated in response to receiving an instruction intended to access the device's configuration data space. A map between the device's configuration data space and the processor's addressable space is accessed, the map having previously mapped the device's configuration data space to one or more pages of the processor's addressable space. Using the map, the request from the processor is translated into a configuration cycle on the interconnect to access the device's configuration data space.

Abstract: An apparatus for generating an inhomogeneous electric field that can produce thrust having a first electrode constructed of a first conducting material, a second electrode constructed of a second conducting material separated from but in proximity of the first electrode and a first and second dielectric material interposed between the first and second electrodes, the first and second dielectric materials having a high and low mass density, respectively.

Abstract: A device for generating an inhomogeneous electrical field includes first and second electrodes. The first electrode may be a portion of a sphere, a cone, a paraboloid, a cylinder; a hollow sphere, a hollow cone, a hollow paraboloid, or a hollow cylinder. The second electrode may be a portion of a sphere, a cone, a paraboloid, a cylinder, a hollow sphere, a hollow cone, a hollow paraboloid or a hollow cylinder. The first and second electrodes are aligned to produce an inhomogeneous electric field when charged with a voltage potential and generate a gravitational effect. The second electrode may be at least partially concentric with said first electrode.

Abstract: Methods and devices for producing inhomogeneous electrical fields are disclosed.