Patents by Inventor Jose De Jesus Pineda De Gyvez

Jose De Jesus Pineda De Gyvez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11163346
    Abstract: An electronic device including a power source providing a source voltage, a capacitor, a primary regulator circuit, an always-on load that is active during a low power mode, and a recycle control circuit. The primary regulator circuit receives the source voltage and has an output that maintains a charge on the capacitor during an active mode. The primary regulator circuit does not contribute to a charge on the capacitor during the low power mode. The recycle control circuit includes a select circuit and a select control circuit. The select circuit selects, based on a control signal, between the voltage of the capacitor and at least one supply voltage including or otherwise developed using the source voltage to provide power to the always-on load during the low power mode. The select control circuit provides the control signal to control power provided to the always-on load during the low power mode.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: November 2, 2021
    Assignee: NXP B.V.
    Inventors: Ajay Kapoor, Kristof Blutman, Juan Diego Echeverri Escobar, Jose de Jesus Pineda de Gyvez, Jurgen Geerlings, Hamed Fatemi
  • Patent number: 10942748
    Abstract: In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: March 9, 2021
    Assignee: NXP B.V.
    Inventors: Surendra Guntur, Sebastien Antonius Josephus Fabrie, Jose de Jesus Pineda de Gyvez
  • Patent number: 10739846
    Abstract: An electronic device includes a digital circuit, a power delivery subsystem configured to provide a supply voltage and a body-biasing voltage to the digital circuit, and a controller a controller coupled to the power delivery subsystem. The controller is configured to determine a process parameter for the electronic device, determine a current temperature parameter for the electronic device, concurrently determine a first coarse-grain level for the supply voltage and a second coarse-grain level for the body-biasing voltage based on the process parameter, the current temperature parameter, and a frequency of a clock signal to be supplied to the digital circuit, and to determine a fine-grain level for the supply voltage.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 11, 2020
    Assignee: NXP B.V.
    Inventors: Ajay Kapoor, Juan Diego Echeverri Escobar, Kristof Blutman, Sebastien Antonius Josephus Fabrie, Jose de Jesus Pineda de Gyvez, Hamed Fatemi
  • Patent number: 10732698
    Abstract: A technique for managing power in an embedded processing system includes generating a workload model for the embedded processing system in response to a control signal, an event status signal, and a reference clock signal. The control signal is received from a peripheral device. The event status signal is received from an event processor configured to control execution of tasks by a processor core of the embedded processing system. The technique includes providing power configuration information to the processor core. The power configuration information corresponds to an operating point selected based on the control signal, the event status signal, the reference clock signal, the workload model, and a predetermined energy model.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 4, 2020
    Assignee: NXP B.V.
    Inventors: Jose de Jesus Pineda de Gyvez, Hamed Fatemi, Manuele Rusci, Luca Benini, Elisabetta Farella, Davide Rossi
  • Publication number: 20200183486
    Abstract: An electronic device includes a digital circuit, a power delivery subsystem configured to provide a supply voltage and a body-biasing voltage to the digital circuit, and a controller a controller coupled to the power delivery subsystem. The controller is configured to determine a process parameter for the electronic device, determine a current temperature parameter for the electronic device, concurrently determine a first coarse-grain level for the supply voltage and a second coarse-grain level for the body-biasing voltage based on the process parameter, the current temperature parameter, and a frequency of a clock signal to be supplied to the digital circuit, and to determine a fine-grain level for the supply voltage.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: Ajay Kapoor, Juan Diego Echeverri Escobar, Kristof Blutman, Sebastien Antonius Josephus Fabrie, Jose de Jesus Pineda de Gyvez, Hamed Fatemi
  • Publication number: 20200090040
    Abstract: An apparatus for processing a signal for input to a neural network, the apparatus configured to: receive a signal comprising a plurality of samples of an analog signal over time; determine at least one frame comprising a group of consecutive samples of the signal, wherein the or each frame includes a first number of samples; for each frame, determine a set of correlation values comprising a second number of correlation values, the second number less than the first number, each correlation value of the set of correlation values based on an autocorrelation of the frame at a plurality of different time lags; provide an output based on the set of correlation values corresponding to the or each of the frames for a neural network for one or more of classification of the analog signal by the neural network and training the neural network based on a predetermined classification.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 19, 2020
    Inventors: Jose de Jesus Pineda de Gyvez, Hamed Fatemi, Emad Ayman Taleb Ibrahim
  • Publication number: 20200073453
    Abstract: An electronic device including a power source providing a source voltage, a capacitor, a primary regulator circuit, an always-on load that is active during a low power mode, and a recycle control circuit. The primary regulator circuit receives the source voltage and has an output that maintains a charge on the capacitor during an active mode. The primary regulator circuit does not contribute to a charge on the capacitor during the low power mode. The recycle control circuit includes a select circuit and a select control circuit. The select circuit selects, based on a control signal, between the voltage of the capacitor and at least one supply voltage including or otherwise developed using the source voltage to provide power to the always-on load during the low power mode. The select control circuit provides the control signal to control power provided to the always-on load during the low power mode.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: Ajay Kapoor, Kristof Blutman, Juan Diego Echeverri Escobar, Jose de Jesus Pineda de Gyvez, Jurgen Geerlings, Hamed Fatemi
  • Publication number: 20190146566
    Abstract: A technique for managing power in an embedded processing system includes generating a workload model for the embedded processing system in response to a control signal, an event status signal, and a reference clock signal. The control signal is received from a peripheral device. The event status signal is received from an event processor configured to control execution of tasks by a processor core of the embedded processing system. The technique includes providing power configuration information to the processor core. The power configuration information corresponds to an operating point selected based on the control signal, the event status signal, the reference clock signal, the workload model, and a predetermined energy model.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Inventors: Jose de Jesus Pineda de Gyvez, Hamed Fatemi, Manuele Rusci, Luca Benini, Elisabetta Farella, Davide Rossi
  • Patent number: 10270448
    Abstract: A level shifter circuit is described herein for shifting a signal from a first voltage domain to a second voltage domain. The level shifter circuit includes two current paths between a supply terminal of the first voltage domain and a supply terminal of the second voltage domain. The first and second current paths each include a differential transistor that receives a signal from a pulse generator in a first voltage domain. The pulse generator provides pulses to the differential transistors based on an input signal to be translated to the second voltage domain. The level shifter includes a latch circuit in the second voltage domain that includes two inputs where each input is biased at a node of one of the current paths. Each current path includes a bias transistor whose control terminal receives a compensated biasing voltage for biasing the bias transistor. The compensated biasing voltage is compensated to account for drive strength variation of at least one transistor in each current path.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 23, 2019
    Assignee: NXP B.V.
    Inventors: Kristof Blutman, Sebastien Antonius Josephus Fabrie, Juan Diego Echeverri Escobar, Ajay Kapoor, Jose de Jesus Pineda de Gyvez, Hamed Fatemi
  • Patent number: 10185910
    Abstract: A control system (100) for controlling a power consumption of an electronic device (300) is provided. The electronic device is adapted to communicate with a reader device via a wireless communication interface. The control system comprises a measuring unit (102) being adapted for measuring an actual field strength of an electromagnetic field provided by the reader device to the control system, a power delivery unit (101) being adapted for delivering power received via the electromagnetic field to the electronic device, and a control unit (103) being coupled to the measuring unit and being adapted for providing a control signal to the electronic device for controlling the consumption of the power being delivered to the electronic device, wherein the control signal is based on the actual field strength of the electromagnetic field.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: January 22, 2019
    Assignee: NXP B.V.
    Inventors: Ajay Kapoor, Gerard Villar Pique, Jose de Jesus Pineda De Gyvez
  • Publication number: 20180300138
    Abstract: A human-machine-interface system comprising: register-file-memory, configured to store input-data; a first-processing-element-slice, a second-processing-element-slice, and a controller. Each of the processing-slices comprise: a register configured to store register-data; and a processing-element configured to apply an arithmetic and logic operation on the register-data in order to provide convolution-output-data. The controller is configured to: load input-data from the register-file-memory into the first-register as the first-register-data; and load: (i) input-data from the register-file-memory, or (ii) the first-register-data from the first-register, into the second-register as the second-register-data.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 18, 2018
    Inventors: Jose de Jesus Pineda de Gyvez, Hamed Fatemi, Gonzalo Moro Pérez, Hendrik Corporaal
  • Patent number: 9996145
    Abstract: A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: June 12, 2018
    Assignee: NXP B.V.
    Inventors: Juan Diego Echeverri Escobar, Jose de Jesus Pineda de Gyvez
  • Patent number: 9960670
    Abstract: One example discloses an apparatus for charge recycling between a first power-domain operating at a first voltage and a second power-domain operating at a second voltage, including: a first power-delivery circuit configured to supply the first voltage to the first power-domain; and a second power-delivery circuit coupled to receive power from both the first power-delivery circuit and the first power-domain; wherein the second power-delivery circuit is configured to supply the second voltage to the second power-domain.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 1, 2018
    Assignee: NXP B.V.
    Inventors: Ajay Kapoor, Kristóf László Blutman, Jose de Jesus Pineda de Gyvez, Hamed Fatemi
  • Publication number: 20170264189
    Abstract: One example discloses an apparatus for charge recycling between a first power-domain operating at a first voltage and a second power-domain operating at a second voltage, including: a first power-delivery circuit configured to supply the first voltage to the first power-domain; and a second power-delivery circuit coupled to receive power from both the first power-delivery circuit and the first power-domain; wherein the second power-delivery circuit is configured to supply the second voltage to the second power-domain.
    Type: Application
    Filed: March 11, 2016
    Publication date: September 14, 2017
    Inventors: Ajay Kapoor, Kristóf László Blutman, Jose de Jesus Pineda de Gyvez, Hamed Fatemi
  • Patent number: 9678564
    Abstract: An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 13, 2017
    Assignee: NXP B.V.
    Inventors: Hamed Fatemi, Ajay Kapoor, Jose de Jesus Pineda de Gyvez, Juan Diego Echeverri Escobar
  • Patent number: 9634649
    Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: April 25, 2017
    Assignee: NXP B.V.
    Inventors: Juan Echeverri Escobar, Jose de Jesus Pineda de Gyvez, Sebastien Antonius Josephus Fabrie
  • Publication number: 20170017486
    Abstract: In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.
    Type: Application
    Filed: July 16, 2015
    Publication date: January 19, 2017
    Applicant: NXP B.V.
    Inventors: Surendra Guntur, Sebastien Antonius Josephus Fabrie, Jose de Jesus Pineda de Gyvez
  • Publication number: 20170012611
    Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.
    Type: Application
    Filed: July 6, 2015
    Publication date: January 12, 2017
    Applicant: NXP B.V.
    Inventors: Juan Echeverri Escobar, Jose de Jesus Pineda de Gyvez, Sebastien Antonius Josephus Fabrie
  • Patent number: 9419592
    Abstract: A sequential circuit arrangement and method are provided in which a latch input signal and a latched version of the input signal are compared to derive a difference signal. This difference signal can detect when changes in the input are not propagated to the output. A second logic gate arrangement derives an error signal from the product of difference signal and a delayed version of the difference signal. This means that normal operation of the circuit is not detected as an error—only when the latched output fails to follow the input after the normally expected delay is the error signal created. The latch element output or an inverted version of the latch element output is selected in dependence on the error signal.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: August 16, 2016
    Assignee: NXP B.V.
    Inventors: Vibhu Sharma, Jose de Jesus Pineda De Gyvez
  • Publication number: 20150346742
    Abstract: A system including: a voltage converter configured to convert a voltage from a power source to a different voltage; a memory coupled to the voltage converter; a digital logic circuit; and a level shifter coupled between the memory and digital logic circuit; wherein leakage current from the memory is stored in a capacitance in the digital logic circuit, wherein the voltage converter is further coupled to a node between the memory and digital logic circuit, and wherein the voltage converter is configured to: monitor a voltage at the node wherein the node has a desired operating voltage value; and adjust the voltage at the node when the voltage at the node varies from the desired operating voltage value.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 3, 2015
    Applicant: NXP B.V.
    Inventors: Ajay Kapoor, Ralf Malzahn, Vibhu Sharma, Jose de Jesus Pineda de Gyvez, Peter Thueringer