Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.

Abstract: A sequential circuit arrangement and method are provided in which a latch input signal and a latched version of the input signal are compared to derive a difference signal. This difference signal can detect when changes in the input are not propagated to the output. A second logic gate arrangement derives an error signal from the product of difference signal and a delayed version of the difference signal. This means that normal operation of the circuit is not detected as an error—only when the latched output fails to follow the input after the normally expected delay is the error signal created. The latch element output or an inverted version of the latch element output is selected in dependence on the error signal.

Abstract: A system including: a voltage converter configured to convert a voltage from a power source to a different voltage; a memory coupled to the voltage converter; a digital logic circuit; and a level shifter coupled between the memory and digital logic circuit; wherein leakage current from the memory is stored in a capacitance in the digital logic circuit, wherein the voltage converter is further coupled to a node between the memory and digital logic circuit, and wherein the voltage converter is configured to: monitor a voltage at the node wherein the node has a desired operating voltage value; and adjust the voltage at the node when the voltage at the node varies from the desired operating voltage value.

Abstract: A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks.

Abstract: A sequential circuit arrangement and method are provided in which a latch input signal and a latched version of the input signal are compared to derive a difference signal. This difference signal can detect when changes in the input are not propagated to the output. A second logic gate arrangement derives an error signal from the product of difference signal and a delayed version of the difference signal. This means that normal operation of the circuit is not detected as an error—only when the latched output fails to follow the input after the normally expected delay is the error signal created. The latch element output or an inverted version of the latch element output is selected in dependence on the error signal.

Abstract: An Analogue to Digital Converter (ADC) having a Gated Ring Voltage Controlled Oscillator, GRVCO, to generate a phase signal according to an input voltage; and a quantization circuit to generate a quantized phase output signal according. The GRVCO operates in either a first or second mode of operation according to a gating control signal. In the first mode of operation, the GRVCO operates in a VCO mode with gating disabled. In the second mode of operation, the GRVCO operates in a GRVCO mode wherein gating is enabled or disabled according to a gating signal.

Abstract: An Analogue to Digital Converter (ADC) having a Gated Ring Voltage Controlled Oscillator, GRVCO, to generate a phase signal according to an input voltage; and a quantization circuit to generate a quantized phase output signal according. The GRVCO operates in either a first or second mode of operation according to a gating control signal. In the first mode of operation, the GRVCO operates in a VCO mode with gating disabled. In the second mode of operation, the GRVCO operates in a GRVCO mode wherein gating is enabled or disabled according to a gating signal.

Abstract: An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.

Abstract: The integrated circuit (10) has an internal power supply domain with a power supply voltage adaptation circuit (14) to adapt the power supply voltage in the power supply domain. Typically, a plurality of such domains is provided wherein the power supply voltage can be adapted independently. During testing an internal power supply voltage is supplied to a temporally integrating analog to digital conversion circuit (16) in the integrating circuit (10). A temporally integrated value of the power supply voltage is measured during a measurement period. Preferably, integrating measurements of a plurality of internal supply voltages are performed in parallel during the same measurement time interval. Preferably a further test is performed by changing over between mutually different supply voltages during a further measurement period. In this way the measured integrated supply voltage can be used to check the speed of the change over between the different voltages.

Abstract: A control system (100) for controlling a power consumption of an electronic device (300) is provided. The electronic device is adapted to communicate with a reader device via a wireless communication interface. The control system comprises a measuring unit (102) being adapted for measuring an actual field strength of an electromagnetic field provided by the reader device to the control system, a power delivery unit (101) being adapted for delivering power received via the electromagnetic field to the electronic device, and a control unit (103) being coupled to the measuring unit and being adapted for providing a control signal to the electronic device for controlling the consumption of the power being delivered to the electronic device, wherein the control signal is based on the actual field strength of the electromagnetic field.

Abstract: An integrated circuit comprises a device under test and embedded test circuitry. The embedded test circuitry comprises a plurality of process monitoring sensors, a threshold circuit for comparing the sensor signals with a threshold window having an upper and a lower limit and a digital interface for outputting the threshold circuit signal. The process monitoring sensors comprise circuitry based on the circuit elements of the device under test. This arrangement enables monitoring of circuit element performance, such as transistor properties, using process monitoring sensors which are embedded with the device under test, so that the same process parameter variations apply to the sensors as to the device under test. The sensors preferably match the physical layout of the device under test.

Abstract: A method of designing a power switch block (200) for an integrated circuit layout in a predefined integrated circuit technology is disclosed. The power switch block (200) includes a segment (710) comprising a plurality of spaced parallel conductors (110, 120, 130, 140) each having a predefined height in said technology, a stack of a first power switch (115) of a first conductivity type and a pair of drivers (152; 154) for respectively driving the first power switch (115) and a second power switch (135), said drivers having predefined dimensions in said technology, and the second switch (135) of a second conductivity type.

Abstract: The present invention relates to a circuit arrangement and method for controlling power supply in an integrated circuit wherein at least one working parameter of at least one electrically isolated circuit region (10) is monitored, and the conductivity of a variable resistor means is locally controlled so as to individually adjust power supply for each of said at least two electrically isolated circuit regions (10) based on the at least one monitored working parameter. Thereby, a fast and simple control functionality with low area overhead can be provided.

Abstract: Test vectors for structural testing of an analog circuit are selected by first selecting an initial set of test input vectors for the analog circuit. A set of faults is selected, comprising faults that each correspond to a respective node in the analog circuit and corresponding fault voltage value for that node. A measure of overlap is computed between probability distributions of test output signal values for the analog circuit in response to the test input vectors in the presence and absence of each of the faults from said set of faults respectively, as a function of estimated statistical spread of component and/or process parameter values in the analog circuit. Test input vectors are selected from the initial set of test input vectors for use in testing on the basis of whether the measure of overlap for at least one if the faults is below a threshold value in response to the selected test input vector under control of the test selection computer.

Abstract: A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.

Abstract: The present invention relates to a circuit arrangement and method for controlling power supply in an integrated circuit wherein at least one working parameter of at least one electrically isolated circuit region (10) is monitored, and the conductivity of a variable resistor means is locally controlled so as to individually adjust power supply for each of said at least two electrically isolated circuit regions (10) based on the at least one monitored working parameter. Thereby, a fast and simple control functionality with low area overhead can be provided.

Abstract: The present invention relates to a method and circuit arrangement for controlling performance of an integrated circuit in response to a monitored performance indicator, wherein power supply of the integrated circuit is controlled based on said performance indicator. At least one of a noise level of the controlled power supply and a clock frequency generated in said integrated circuit is monitored and a respective control signal is fed back to the controlling function if the checking result is not within a predetermined range. Thereby, an simple and easily extendable automatic adaptation to process variations can be achieved.

Abstract: A method of designing a power switch block (200) for an integrated circuit layout in a predefined integrated circuit technology is disclosed. The power switch block (200) includes a segment (710) comprising a plurality of spaced parallel conductors (110, 120, 130, 140) each having a predefined height in said technology, a stack of a first power switch (115) of a first conductivity type and a pair of drivers (152; 154) for respectively driving the first power switch (115) and a second power switch (135), said drivers having predefined dimensions in said technology, and the second switch (135) of a second conductivity type.

Abstract: The present invention relates to a method and circuit arrangement for determining power supply noise of a power distribution network. The power supply noise is determined by measuring the propagation delay of a delay circuit powered by the power distribution network, wherein the result of the measuring step is used as an indicator of the power supply noise. Thereby, a real-time power supply noise monitoring can be carried out at any point of a power distribution network of an observed circuitry.

Abstract: A digital system 1 comprises receiving means (5) for receiving one or more performance indicators or parameters from software (6) controlling the execution of an application (3). Based on the performance indicators received by the receiving means (5), a tuning circuit (7) is provided for tuning the frequency (f), supply voltage (Vdd) and/or the transistor threshold voltage (Vb) of the digital system (1). In addition, pipeline configuration means (8) are provided for configuring the pipeline of the digital system (1) based on a pipeline depth determined by selecting means (10). The selecting means (10) is configured to select the pipeline depth (Pd) based on the frequency (f), supply voltage (Vdd), transistor threshold voltage (Vb), and according to whether the application requires maximum throughput or minimum latency.