Patents by Inventor Jose Nunes

Jose Nunes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250227089
    Abstract: A system generates vector representations of entries of traffic logs generated by a firewall. A first model learns contexts of values recorded in the logs during training, and the system extracts vector representations of the values from the trained model. For each log entry, vectors created for the corresponding values are combined to create a vector representing the entry. Cluster analysis of the vector representations can be performed to determine clusters of similar traffic and outliers indicative of potentially anomalous traffic. The system also generates a formal model representing firewall behavior which comprises formulas generated from the firewall rules. Proposed traffic scenarios not recorded in the logs can be evaluated based on the formulas to determine actions which the firewall would take in the scenarios. The combination of models which implement machine learning and formal techniques facilitates evaluation of both observed and hypothetical network traffic based on the firewall rules.
    Type: Application
    Filed: March 27, 2025
    Publication date: July 10, 2025
    Inventors: Charanraj Thimmisetty, Praveen Tiwari, Viswesh Ananthakrishnan, Claudionor Jose Nunes Coelho, JR.
  • Publication number: 20250225376
    Abstract: Multimodal Data Loss Protection (DLP) includes receiving an input comprising data in any of a plurality of formats; processing the input to determine whether or not the data includes sensitive data; and responsive to the input including sensitive data, performing steps of: processing the input to classify the input into a category of a plurality of categories; and providing an indication of the category of the plurality of categories. Advantageously, the trained multimodal system can detect categories of data being accessed, transferred, etc., without the requirement of up-front dictionaries from corporate Information Technology (IT).
    Type: Application
    Filed: February 22, 2024
    Publication date: July 10, 2025
    Applicant: Zscaler, Inc.
    Inventors: Chenhui Hu, Kabir Nagpal, Miao Zhang, Rex Shang, Jacob Bollinger, Arun Bhallamudi, Claudionor Jose Nunes Coelho, JR., Sanjay Kalra
  • Publication number: 20250225412
    Abstract: Systems and methods for next generation artificial intelligence agents include operating an Artificial Intelligence (AI) agent system that includes an agent core connected to memory, one or more tools, and a planner; receiving a request from a user; utilizing the planner to break the request down into a plurality of sub-parts that are each individually simpler than the request; and generating an answer to the request using the plurality of sub-parts with the memory and the one or more tools.
    Type: Application
    Filed: April 19, 2024
    Publication date: July 10, 2025
    Applicant: Zscaler, Inc.
    Inventors: Claudionor Jose Nunes Coelho, Jr., Guangyu Zhu, Hanchen Xiong, Tushar Karayil, Sree Koratala, Rex Shang, Jacob Bollinger, Mohamed Shabar, Syam Nair
  • Patent number: 12278802
    Abstract: A system generates vector representations of entries of traffic logs generated by a firewall. A first model learns contexts of values recorded in the logs during training, and the system extracts vector representations of the values from the trained model. For each log entry, vectors created for the corresponding values are combined to create a vector representing the entry. Cluster analysis of the vector representations can be performed to determine clusters of similar traffic and outliers indicative of potentially anomalous traffic. The system also generates a formal model representing firewall behavior which comprises formulas generated from the firewall rules. Proposed traffic scenarios not recorded in the logs can be evaluated based on the formulas to determine actions which the firewall would take in the scenarios. The combination of models which implement machine learning and formal techniques facilitates evaluation of both observed and hypothetical network traffic based on the firewall rules.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: April 15, 2025
    Assignee: Palo Alto Networks, Inc.
    Inventors: Charanraj Thimmisetty, Praveen Tiwari, Viswesh Ananthakrishnan, Claudionor Jose Nunes Coelho, Jr.
  • Publication number: 20240232594
    Abstract: Methods, systems, and apparatus, including computer-readable media, are described for globally tuning and generating ML hardware accelerators. A design system selects an architecture representing a baseline processor configuration. An ML cost model of the system generates performance data about the architecture at least by modeling how the architecture executes computations of a neural network that includes multiple layers. Based on the performance data, the architecture is dynamically tuned to satisfy a performance objective when the architecture implements the neural network and executes machine-learning computations for a target application. In response to dynamically tuning the architecture, the system generates a configuration of an ML accelerator that specifies customized hardware configurations for implementing each of the multiple layers of the neural network.
    Type: Application
    Filed: May 3, 2021
    Publication date: July 11, 2024
    Inventors: Yang Yang, Claudionor Jose Nunes Coelho, Jr., Hao Zhuang, Aki Oskari Kuusela
  • Publication number: 20240220867
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for scheduling operations represented on a computation graph. One of the methods comprises receiving data representing a neural network comprising a plurality of layers arranged in a sequence; selecting one or more groups of layers each comprising one or more layers adjacent to each other in the sequence; generating a new machine learning model, comprising: for each group of layers, a respective decision tree that replaces the group of layers, wherein the respective decision tree receives as input a quantized version of the inputs to a respective first layer in the group and generates as output a quantized version of the outputs of a respective last layer in the group, wherein a tree depth of the respective decision tree is based at least in part on a number of layers of the group.
    Type: Application
    Filed: May 10, 2021
    Publication date: July 4, 2024
    Inventors: Claudionor Jose Nunes Coelho, Jr., Aki Oskari Kuusela, Satrajit Chatterjee, Piotr Zielinski, Hao Zhuang
  • Publication number: 20230229895
    Abstract: Systems and methods for producing a neural network architecture with improved energy consumption and performance tradeoffs are disclosed, such as would be deployed for use on mobile or other resource-constrained devices. In particular, the present disclosure provides systems and methods for searching a network search space for joint optimization of a size of a layer of a reference neural network model (e.g., the number of filters in a convolutional layer or the number of output units in a dense layer) and of the quantization of values within the layer. By defining the search space to correspond to the architecture of a reference neural network model, examples of the disclosed network architecture search can optimize models of arbitrary complexity. The resulting neural network models are able to be run using relatively fewer computing resources (e.g., less processing power, less memory usage, less power consumption, etc.), all while remaining competitive with or even exceeding the performance (e.g.
    Type: Application
    Filed: June 2, 2021
    Publication date: July 20, 2023
    Inventors: Claudionor Jose Nunes Coelho, Jr., Piotr Zielinski, Aki Kuusela, Shan Li, Hao Zhuang
  • Publication number: 20230130091
    Abstract: Provided is a release device including a housing having an inlet and an outlet, a heating element arranged in the housing, a first fan arranged to move air into the inlet and around the heating element, and a second fan arranged to move vapor out of the outlet. Other embodiments and arrangements are disclosed.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 27, 2023
    Inventors: Fadhil Yussof Musa, Fernando José Nunes Antunes, João Manuel Pires da Silva
  • Publication number: 20230123157
    Abstract: The present application discloses a method, system, and computer system for determining whether to train a machine learning model. The method includes analyzing a set of data for temporal drift detection, determining that a resultant stationary series has changed from training data, and in response to determining that the resultant stationary series has changed, automatically updating the machine learning model, wherein the machine learning model is trained based at least in part on a set of training data.
    Type: Application
    Filed: January 21, 2022
    Publication date: April 20, 2023
    Inventors: Nandini Ramanan, Claudionor Jose Nunes Coelho Junior
  • Publication number: 20230080654
    Abstract: Identifying causal relationships between outlier telemetry events in telemetry metric data using machine learning ensembles of an autoencoder and an attention mechanism provides an automated framework for root cause analysis. Outlier telemetry events are detected across a cloud of telemetry events using unsupervised learning models. To establish a causal relationship between outlier telemetry events, autoencoder/attention mechanism ensembles are trained for pairs of telemetry metrics. When inputs of sequences of telemetry events of a first telemetry metric and a second telemetry metric to the ensemble have sufficiently high loss value, a causal relationship is inferred. Internal node values of the attention mechanism from the input identify specific time stamps for the first telemetry metric that have a causal relationship with the outlier telemetry event.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Inventors: Zhen Han Si, Claudionor Jose Nunes Coelho, JR., Viswesh Ananthakrishnan, Eyal Firstenberg
  • Publication number: 20220385635
    Abstract: A system generates vector representations of entries of traffic logs generated by a firewall. A first model learns contexts of values recorded in the logs during training, and the system extracts vector representations of the values from the trained model. For each log entry, vectors created for the corresponding values are combined to create a vector representing the entry. Cluster analysis of the vector representations can be performed to determine clusters of similar traffic and outliers indicative of potentially anomalous traffic. The system also generates a formal model representing firewall behavior which comprises formulas generated from the firewall rules. Proposed traffic scenarios not recorded in the logs can be evaluated based on the formulas to determine actions which the firewall would take in the scenarios. The combination of models which implement machine learning and formal techniques facilitates evaluation of both observed and hypothetical network traffic based on the firewall rules.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 1, 2022
    Inventors: Charanraj Thimmisetty, Praveen Tiwari, Viswesh Ananthakrishnan, Claudionor Jose Nunes Coelho, JR.
  • Publication number: 20220143246
    Abstract: A sterilization particle includes a porous carrier material having at least one of the following: a microporous material, a mesoporous material, a macroporous material, or a combination thereof; and a sterilization material contained in pores of the porous carrier material or adsorbed on a surface of the porous carrier material. The sterilization material includes at least 4 weight percent of the sterilization particle. A sterilization device, a method for preparing a sterilization particle, and a method for sterilizing a space are also disclosed.
    Type: Application
    Filed: February 19, 2020
    Publication date: May 12, 2022
    Inventors: Fadhil Yussof Musa, Fernando José Nunes Antunes, João Manuel Pires da Silva
  • Patent number: 11112682
    Abstract: A stand in which professional television cameras are placed includes a compact and easily storable and transportable stand for professional television cameras comprising a plurality of supporting legs pivotable upon the fixed base, and between a folded position, in which the stand is positioned coupled to a corresponding slot, and an open position, in which the stand is positioned substantially in parallel to the fixed base and thereby able to be placed on a surface. When the stand is in storage or transport, the stand may be brought into a folded position, in which each supporting leg is coupled to a corresponding slot, reducing the form factor of the stand while folded and having higher easiness in transportation.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: September 7, 2021
    Assignee: OmniCam4Sky, Lda.
    Inventors: Jorge Manuel Quinta Gaspar, Paulo José Nunes Guerreiro
  • Patent number: 10078042
    Abstract: The present invention refers to a method wherein a test body is assembled in specific configurations to be submitted to testing in a conventional hydrostatic chamber. The method calls for assembling a test body that simulates cementing failures, the presence of stress anisotropy and a borehole of irregular geometry, by pressurizing said test body in a conventional hydrostatic chamber. The uniform forces are distributed circumferentially around a casing stream in a non-uniform way, simulating operating conditions that are as close as possible to reality, enabling an analysis of how the structure reacts in scenarios similar to actual conditions.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 18, 2018
    Assignee: PETRÓLEO BRASILEIRO S.A.—PETROBRAS
    Inventors: Edgard Poiate Junior, Jose Nunes Pimentel Neto, Fernando Antonio Santos Medeiros, Alvaro Maia Da Costa, Jose Luiz Falcão, Claudio Dos Santos Amaral, Renato Seixas Da Rocha
  • Patent number: 9934410
    Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: April 3, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Jose Nunes Coelho
  • Patent number: 9922209
    Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: March 20, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Jose Nunes Coelho
  • Patent number: 9817930
    Abstract: Various mechanisms identify an electronic design model and determine a data propagation diagram by receiving a set of path property sources or destinations, determine a set of helper properties for the data propagation diagram by traversing at least a portion of the data propagation diagram, and verify the electronic design model by examining one or more helper properties and determining verification of the one or more helper properties leads to concrete results to generate verification results. Data propagation diagrams may be annotated with verification results to show verification progresses, highlight sources of complexity, and be further synchronized with waveform displays of one or more traces. Search space may be trimmed during a verification flow to enhance performance of verification engine(s). New start states closer to the final state than the default state may be identified during verification and used to enhance performance of the verification engine.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: November 14, 2017
    Assignee: Cadence Design Systems Inc.
    Inventors: Caio Araujo Texeira Campos, Tamires Vargas Campanema Franco Santos, Andrea Iabrudi Tavares, Fabiano Peixoto, Claudionor Jose Nunes Coelho, Jr.
  • Patent number: 9659142
    Abstract: Disclosed are techniques for implementing trace warping for electronic designs. These techniques identify a portion of an electronic design including a set of signals of interest corresponding to a plurality of simulation combinations over a range of clock cycles in a trace display. A pair of matching simulation combinations is identified from one or more pairs of matching simulation combinations for the set of signals of interest; and a first clock cycle and a second clock cycle corresponding to the pair of matching simulation combinations are identified in the range of clock cycles. A plurality of clock cycles between the first clock cycle and the second clock cycle can be compressed in the trace display.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: May 23, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Claudionor Jose Nunes Coelho, Jr., Chung-Wah Norris Ip, Thiago Radicchi Roque
  • Patent number: 9449196
    Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: September 20, 2016
    Assignee: Jasper Design Automation, Inc.
    Inventors: Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Jose Nunes Coelho
  • Patent number: 9081927
    Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: July 14, 2015
    Assignee: JASPER DESIGN AUTOMATION, INC.
    Inventors: Claudionor José Nunes Coelho, Jr., Chien-Liang Lin, Chung-Wah Norris Ip