Patents by Inventor Jose Nunes
Jose Nunes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230277718Abstract: The present disclosure relates to a wound treatment dressing in which an absorbent layer comprises an odour-inhibiting mixture; wherein the odour-inhibiting mixture comprises coffee grounds. More particularly, a wound treatment dressing is provided for the absorption of odours in wounds, including pressure ulcers, leg ulcers, cancerous wounds, diabetic foot ulcers, burns, traumatic or surgical wounds, which comprises an odour-inhibiting mixture with coffee grounds.Type: ApplicationFiled: May 18, 2021Publication date: September 7, 2023Inventors: Filipe José NUNES AGOSTINHO, Paulo Jorge GARCIA FRADE
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Publication number: 20230229895Abstract: Systems and methods for producing a neural network architecture with improved energy consumption and performance tradeoffs are disclosed, such as would be deployed for use on mobile or other resource-constrained devices. In particular, the present disclosure provides systems and methods for searching a network search space for joint optimization of a size of a layer of a reference neural network model (e.g., the number of filters in a convolutional layer or the number of output units in a dense layer) and of the quantization of values within the layer. By defining the search space to correspond to the architecture of a reference neural network model, examples of the disclosed network architecture search can optimize models of arbitrary complexity. The resulting neural network models are able to be run using relatively fewer computing resources (e.g., less processing power, less memory usage, less power consumption, etc.), all while remaining competitive with or even exceeding the performance (e.g.Type: ApplicationFiled: June 2, 2021Publication date: July 20, 2023Inventors: Claudionor Jose Nunes Coelho, Jr., Piotr Zielinski, Aki Kuusela, Shan Li, Hao Zhuang
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Publication number: 20230130091Abstract: Provided is a release device including a housing having an inlet and an outlet, a heating element arranged in the housing, a first fan arranged to move air into the inlet and around the heating element, and a second fan arranged to move vapor out of the outlet. Other embodiments and arrangements are disclosed.Type: ApplicationFiled: December 18, 2020Publication date: April 27, 2023Inventors: Fadhil Yussof Musa, Fernando José Nunes Antunes, João Manuel Pires da Silva
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Publication number: 20230123157Abstract: The present application discloses a method, system, and computer system for determining whether to train a machine learning model. The method includes analyzing a set of data for temporal drift detection, determining that a resultant stationary series has changed from training data, and in response to determining that the resultant stationary series has changed, automatically updating the machine learning model, wherein the machine learning model is trained based at least in part on a set of training data.Type: ApplicationFiled: January 21, 2022Publication date: April 20, 2023Inventors: Nandini Ramanan, Claudionor Jose Nunes Coelho Junior
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Publication number: 20230080654Abstract: Identifying causal relationships between outlier telemetry events in telemetry metric data using machine learning ensembles of an autoencoder and an attention mechanism provides an automated framework for root cause analysis. Outlier telemetry events are detected across a cloud of telemetry events using unsupervised learning models. To establish a causal relationship between outlier telemetry events, autoencoder/attention mechanism ensembles are trained for pairs of telemetry metrics. When inputs of sequences of telemetry events of a first telemetry metric and a second telemetry metric to the ensemble have sufficiently high loss value, a causal relationship is inferred. Internal node values of the attention mechanism from the input identify specific time stamps for the first telemetry metric that have a causal relationship with the outlier telemetry event.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Inventors: Zhen Han Si, Claudionor Jose Nunes Coelho, JR., Viswesh Ananthakrishnan, Eyal Firstenberg
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Publication number: 20220385635Abstract: A system generates vector representations of entries of traffic logs generated by a firewall. A first model learns contexts of values recorded in the logs during training, and the system extracts vector representations of the values from the trained model. For each log entry, vectors created for the corresponding values are combined to create a vector representing the entry. Cluster analysis of the vector representations can be performed to determine clusters of similar traffic and outliers indicative of potentially anomalous traffic. The system also generates a formal model representing firewall behavior which comprises formulas generated from the firewall rules. Proposed traffic scenarios not recorded in the logs can be evaluated based on the formulas to determine actions which the firewall would take in the scenarios. The combination of models which implement machine learning and formal techniques facilitates evaluation of both observed and hypothetical network traffic based on the firewall rules.Type: ApplicationFiled: September 13, 2021Publication date: December 1, 2022Inventors: Charanraj Thimmisetty, Praveen Tiwari, Viswesh Ananthakrishnan, Claudionor Jose Nunes Coelho, JR.
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Publication number: 20220143246Abstract: A sterilization particle includes a porous carrier material having at least one of the following: a microporous material, a mesoporous material, a macroporous material, or a combination thereof; and a sterilization material contained in pores of the porous carrier material or adsorbed on a surface of the porous carrier material. The sterilization material includes at least 4 weight percent of the sterilization particle. A sterilization device, a method for preparing a sterilization particle, and a method for sterilizing a space are also disclosed.Type: ApplicationFiled: February 19, 2020Publication date: May 12, 2022Inventors: Fadhil Yussof Musa, Fernando José Nunes Antunes, João Manuel Pires da Silva
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Patent number: 11112682Abstract: A stand in which professional television cameras are placed includes a compact and easily storable and transportable stand for professional television cameras comprising a plurality of supporting legs pivotable upon the fixed base, and between a folded position, in which the stand is positioned coupled to a corresponding slot, and an open position, in which the stand is positioned substantially in parallel to the fixed base and thereby able to be placed on a surface. When the stand is in storage or transport, the stand may be brought into a folded position, in which each supporting leg is coupled to a corresponding slot, reducing the form factor of the stand while folded and having higher easiness in transportation.Type: GrantFiled: June 19, 2020Date of Patent: September 7, 2021Assignee: OmniCam4Sky, Lda.Inventors: Jorge Manuel Quinta Gaspar, Paulo José Nunes Guerreiro
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Patent number: 10078042Abstract: The present invention refers to a method wherein a test body is assembled in specific configurations to be submitted to testing in a conventional hydrostatic chamber. The method calls for assembling a test body that simulates cementing failures, the presence of stress anisotropy and a borehole of irregular geometry, by pressurizing said test body in a conventional hydrostatic chamber. The uniform forces are distributed circumferentially around a casing stream in a non-uniform way, simulating operating conditions that are as close as possible to reality, enabling an analysis of how the structure reacts in scenarios similar to actual conditions.Type: GrantFiled: December 22, 2011Date of Patent: September 18, 2018Assignee: PETRÓLEO BRASILEIRO S.A.—PETROBRASInventors: Edgard Poiate Junior, Jose Nunes Pimentel Neto, Fernando Antonio Santos Medeiros, Alvaro Maia Da Costa, Jose Luiz Falcão, Claudio Dos Santos Amaral, Renato Seixas Da Rocha
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Patent number: 9934410Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.Type: GrantFiled: September 19, 2016Date of Patent: April 3, 2018Assignee: Cadence Design Systems, Inc.Inventors: Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Jose Nunes Coelho
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Patent number: 9922209Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.Type: GrantFiled: September 19, 2016Date of Patent: March 20, 2018Assignee: Cadence Design Systems, Inc.Inventors: Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Jose Nunes Coelho
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Patent number: 9817930Abstract: Various mechanisms identify an electronic design model and determine a data propagation diagram by receiving a set of path property sources or destinations, determine a set of helper properties for the data propagation diagram by traversing at least a portion of the data propagation diagram, and verify the electronic design model by examining one or more helper properties and determining verification of the one or more helper properties leads to concrete results to generate verification results. Data propagation diagrams may be annotated with verification results to show verification progresses, highlight sources of complexity, and be further synchronized with waveform displays of one or more traces. Search space may be trimmed during a verification flow to enhance performance of verification engine(s). New start states closer to the final state than the default state may be identified during verification and used to enhance performance of the verification engine.Type: GrantFiled: December 31, 2014Date of Patent: November 14, 2017Assignee: Cadence Design Systems Inc.Inventors: Caio Araujo Texeira Campos, Tamires Vargas Campanema Franco Santos, Andrea Iabrudi Tavares, Fabiano Peixoto, Claudionor Jose Nunes Coelho, Jr.
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Patent number: 9659142Abstract: Disclosed are techniques for implementing trace warping for electronic designs. These techniques identify a portion of an electronic design including a set of signals of interest corresponding to a plurality of simulation combinations over a range of clock cycles in a trace display. A pair of matching simulation combinations is identified from one or more pairs of matching simulation combinations for the set of signals of interest; and a first clock cycle and a second clock cycle corresponding to the pair of matching simulation combinations are identified in the range of clock cycles. A plurality of clock cycles between the first clock cycle and the second clock cycle can be compressed in the trace display.Type: GrantFiled: October 6, 2015Date of Patent: May 23, 2017Assignee: Cadence Design Systems, Inc.Inventors: Claudionor Jose Nunes Coelho, Jr., Chung-Wah Norris Ip, Thiago Radicchi Roque
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Patent number: 9449196Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.Type: GrantFiled: April 22, 2013Date of Patent: September 20, 2016Assignee: Jasper Design Automation, Inc.Inventors: Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Jose Nunes Coelho
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Patent number: 9081927Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.Type: GrantFiled: October 4, 2013Date of Patent: July 14, 2015Assignee: JASPER DESIGN AUTOMATION, INC.Inventors: Claudionor José Nunes Coelho, Jr., Chien-Liang Lin, Chung-Wah Norris Ip
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Publication number: 20150191445Abstract: The present invention relates to acyl-hydrazone compounds, in particular 3,4,5-trimethoxyphenyl-hydrazide derivatives, as well as the oxadiazole analogs thereof and other similar compounds, and to the pharmaceutical use of the same for the treatment of various diseases associated with cell proliferation, such as leukemias, including acute lymphoblastic leukemia (ALL), tumours and inflammation. Acyl-hydrazones have been obtained having activity similar to that of the compound used as a standard in experiments (colchicine). The greater selectivity of the compounds according to the invention is an important feature, associated with fewer side effects than the pharmaceuticals used at present in clinical treatments.Type: ApplicationFiled: November 26, 2012Publication date: July 9, 2015Inventors: Ricardo Jose Nunes, Alessandra Mascarello, Rosendo Augusto Yunes, Taisa Regina Stumpf, Paulo Cesar Leal, Jose Andres Yunes, Carolina Pereira de Souza Melo, Rafael Renatino Canevarolo, Louise Domeneghini Chiaradia, Andre Bortolini Silveira, Angelo Brunelli Albertoni Laranjeira
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Publication number: 20150101397Abstract: The present invention refers to a method wherein a test body is assembled in specific configurations to be submitted to testing in a conventional hydrostatic chamber. The method calls for assembling a test body that simulates cementing failures, the presence of stress anisotropy and a borehole of irregular geometry, by pressurizing said test body in a conventional hydrostatic chamber. The uniform forces are distributed circumferentially around a casing stream in a non-uniform way, simulating operating conditions that are as close as possible to reality, enabling an analysis of how the structure reacts in scenarios similar to actual conditions.Type: ApplicationFiled: December 22, 2011Publication date: April 16, 2015Applicant: PETRÓLEO BRASILEIRO S.A. - PETROBRASInventors: Edgard Poiate Junior, Jose Nunes Pimentel Neto, Fernando Antonio Santos Medeiros, Alvaro Maia Da Costa, Jose Luiz Falcão, Claudio Dos Santos Amaral, Renato Seixas Da Rocha
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Publication number: 20150100933Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.Type: ApplicationFiled: October 9, 2013Publication date: April 9, 2015Applicant: Jasper Design Automation, Inc.Inventors: Claudionor José Nunes Coelho, JR., Chien-Liang Lin, Chung-Wah Norris Ip
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Publication number: 20150100932Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.Type: ApplicationFiled: October 4, 2013Publication date: April 9, 2015Applicant: Jasper Design Automation, Inc.Inventors: Claudionor José Nunes Coelho, JR., Chien-Liang Lin, Chung-Wah Norris Ip
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Patent number: 8990745Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.Type: GrantFiled: October 9, 2013Date of Patent: March 24, 2015Assignee: Jasper Design Automation, Inc.Inventors: Claudionor José Nunes Coelho, Chien-Liang Lin, Chung-Wah Norris Ip