Patents by Inventor Jose Nunes

Jose Nunes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8643995
    Abstract: A method and device for protecting an electric system against overvoltage occurrences, the electric system being adapted to be subjected to voltages. The device includes a plurality of surge arresters and a detector configured to detect overvoltage occurrences in the electric system. The surge arresters are connected in series, the plurality of surge arresters including a first surge arrester which is connectable to ground and a second surge arrester which is connectable to the electric system which is to be protected. The device includes a switch connected in parallel with at least one surge arrester of the plurality of surge arresters, and the switch is adapted to be open when no overvoltage occurrence is detected and adapted to close upon overvoltage occurrence detection and short-circuit the surge arrester with which it is connected in parallel. An electric system includes at least one such device.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: February 4, 2014
    Assignee: ABB Technology AG
    Inventors: Jose Nunes, Jonas Karlsson
  • Patent number: 8572527
    Abstract: An analysis tool that generates properties for a circuit design. The debugging tool receives a circuit design encoded in a hardware description language. The tool identifies portions of the circuit design that correspond to features of interest (e.g., counters, finite state machines, one hot vectors, etc) in the circuit design. Each portion of the circuit design has a cone of influence, and the tool identifies control signals from within the cones of influence. By identifying control signals in this manner, the tool can then generate the properties based on values for the control signals and the identified portions of the circuit design that are obtained from data describing the operation of the circuit design over a number of clock cycles (e.g., simulation data). The result is one or more properties that are likely to represent a relevant behavior of the circuit design.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: October 29, 2013
    Assignee: Jasper Design Automation, Inc.
    Inventors: Claudionor José Nunes Coelho, Jr., Fabiano Cruz Peixoto
  • Patent number: 8527911
    Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: September 3, 2013
    Assignee: Jasper Design Automation, Inc.
    Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Georgia Penido Safe, Claudionor José Nunes Coelho, Yann Alain Antonioli
  • Patent number: 8458621
    Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: June 4, 2013
    Assignee: Jasper Design Automation, Inc.
    Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Georgia Penido Safe, Claudionor José Nunes Coelho, Yann Alain Antonioli
  • Publication number: 20120218672
    Abstract: A method and device for protecting an electric system against overvoltage occurrences, the electric system being adapted to be subjected to voltages. The device includes a plurality of surge arresters and a detector configured to detect overvoltage occurrences in the electric system. The surge arresters are connected in series, the plurality of surge arresters including a first surge arrester which is connectable to ground and a second surge arrester which is connectable to the electric system which is to be protected. The device includes a switch connected in parallel with at least one surge arrester of the plurality of surge arresters, and the switch is adapted to be open when no overvoltage occurrence is detected and adapted to close upon overvoltage occurrence detection and short-circuit the surge arrester with which it is connected in parallel. An electric system includes at least one such device.
    Type: Application
    Filed: August 31, 2009
    Publication date: August 30, 2012
    Applicant: ABB TECHNOLOGY AG
    Inventors: Jose Nunes, Jonas Karlsson
  • Patent number: 8205187
    Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: June 19, 2012
    Assignee: Jasper Design Automation, Inc.
    Inventors: Claudionor José Nunes Coelho, Chung-Wah Norris Ip, Harry David Foster, Rajeev Kumar Ranjan, Kathryn Drews Kranen, Georgia Penido Safe
  • Publication number: 20070002448
    Abstract: An optical device generated by interferometric lithography, in the form of a surface relief pattern that diffracts light, to be used mainly in optical security, produced by optical systems compliant with the Schimpflug and hinge Rules containing: two identical lenses L1 and L2, two physical object location B1 e B2 and one image plane A1?A2. No physical mask is needed throughout the origination process, thus eliminating any kind of border effects. The device actually implements an in-plane focused hologram, with a complex surface pattern of valleys and ridges with a non-trivial generating function, which is, by itself, both an additional security feature of the device and its fingerprint. The time to generate the optical device is proportional to the number of colours specified for the reference geometry and not depend on the overall area of the optical device.
    Type: Application
    Filed: March 25, 2003
    Publication date: January 4, 2007
    Inventors: Jose Nunes Vicente Rebordao, Alexandre Pereira Cabral
  • Patent number: 5074927
    Abstract: A process for the production of strips and plates of ferritic stainless steel containing Nb, which are hot rolled and annealed continuously so as to obtain a metallurgical structure such that, after conventional cold rolling, the resulting product has improved characteristics of medium and deep stamping characteristics. The last pass of the rough rolling stage is effected at a temperature between 900.degree. and 950.degree. C. with reductions of 35 to 50%. In the last pass of the finishing mill operates at temperatures lower than 900.degree. C. and a deformation of greater than 35%. The resulting coil is then annealed in a single heat treatment in a continuous furnace at temperatures between 900.degree. and 1100.degree. C.
    Type: Grant
    Filed: August 22, 1990
    Date of Patent: December 24, 1991
    Assignee: Cia. Acos Especiais Itabira - Acesita
    Inventors: Valentim A. Rodrigues, Ronaldo C. Ribeiro da Silva, Ronaldo A. N. Marques Barbosa, Jose Nunes de Carvalho, Jose N. da Silva