Patents by Inventor Jose P. Pereira

Jose P. Pereira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6700809
    Abstract: Entry relocation in a content addressable memory (CAM) device. The CAM device is instructed to store a first value and to supply an address at which the first value is stored. If the address indicates that the first value has been stored within an overflow storage array of the CAM device, the CAM device is instructed to store the first value again.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: March 2, 2004
    Assignee: NetLogic Microsystems, Inc.
    Inventors: David W. Ng, Sunder R. Rathnavelu, Jose P. Pereira
  • Patent number: 6697276
    Abstract: A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: February 24, 2004
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Jose P. Pereira, Sunder R. Rathnavelu, Rodolfo G. Beraha, Lewis M. Carroll, Ronald S. Jankov
  • Publication number: 20030123270
    Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.
    Type: Application
    Filed: February 11, 2003
    Publication date: July 3, 2003
    Inventors: Jose P. Pereira, Varadarajan Srinivasan
  • Patent number: 6542391
    Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: April 1, 2003
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Jose P. Pereira, Varadarajan Srinivasan
  • Publication number: 20020161969
    Abstract: A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.
    Type: Application
    Filed: October 31, 2001
    Publication date: October 31, 2002
    Inventors: Bindiganavale S. Nataraj, Nilesh A. Gharia, Rupesh R. Roy, Jose P. Pereira, Varadarajan Srinivasan, Sandeep Khanna, Hok F. Wong
  • Publication number: 20020129198
    Abstract: A content addressable memory (CAM) device comprising a plurality of CAM blocks and a block control circuit. The plurality of CAM blocks each includes an array of CAM cells to store data words and an array of priority number storage circuits to store priority numbers. Each priority number indicates a priority of a respective one of the data words relative to others of the data words. The block control circuit has an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each select signal selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to the class code.
    Type: Application
    Filed: October 31, 2001
    Publication date: September 12, 2002
    Inventors: Bindiganavale S. Nataraj, Nilesh A. Gharia, Rupesh R. Roy, Jose P. Pereira, Varadarajan Srinivasan, Sandeep Khanna, Hok F. Wong
  • Publication number: 20020075714
    Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.
    Type: Application
    Filed: August 27, 2001
    Publication date: June 20, 2002
    Inventors: Jose P. Pereira, Varadarajan Srinivasan