Abstract: A shoe comprising a sole. The sole includes a midsole including multiple midsole portions. A first midsole portion is an inner portion of a first midsole material. A second, midsole portion of a second midsole material circumscribes the first midsole portion, and a third midsole portion formed of a third midsole material circumscribes the second midsole portion. The second midsole portion has a greater durometer hardness than the first midsole portion. The third midsole portion has a different durometer hardness than the second midsole portion. The second midsole portion is of a different color than each of the first midsole portion and the third midsole portion.

Abstract: Techniques for improving efficiency of a switched-capacitor voltage regulator are provided. In an example, a switched-capacitor voltage regulator can include a switched-capacitor network having multiple gain configurations, a clock configured to switch capacitors of the switched-capacitor network between a charge state and a discharge state to provide a scaled output voltage, and a controller configured to select a capacitor configuration associated with a gain of the multiple gain configurations to provide the scaled output voltage within a desired output voltage range while continuously switching the capacitor configuration, and to interrupt switching of the capacitor configuration to permit an output voltage of the switched-capacitor voltage regulator to fall below the scaled output voltage but to remain above a lower limit of the desired output voltage range to save power by reducing losses due to the switching.

Abstract: A line driver circuit is configured to provide a high spurious free dynamic range output and includes first and second output transistors and a control circuit. The first output transistor is controllable to pull an output node to a logic high state, and the second output transistor is controllable to pull the output node to a logic low state. The first control circuit is connected to a control input of the first output transistor and configured to establish a control signal at the control input of the first output transistor while the second output transistor is in a low impedance operating state to reduce an imbalance in turn-on delay between the first output transistor and the second output transistor.

Abstract: A power management unit comprises a controller, an oscillator circuit, and a monitoring circuit. The controller is configured to control operation of a power converter circuit in a low power mode and an active mode. The oscillator circuit is configured to generate clock signals in the low power mode to control the operation of the power converter circuit. The monitoring is circuit configured when in the low power mode to receive a regulated output voltage from the power converter circuit, compare the regulated output voltage to a specified voltage threshold, and turn off the oscillator circuit when the regulated output voltage is greater than the specified threshold voltage and turn on the oscillator circuit when the regulated output voltage is less than the specified threshold voltage.

Abstract: A power management unit comprises a controller, an oscillator circuit, and a monitoring circuit. The controller is configured to control operation of a power converter circuit in a low power mode and an active mode. The oscillator circuit is configured to generate clock signals in the low power mode to control the operation of the power converter circuit. The monitoring is circuit configured when in the low power mode to receive a regulated output voltage from the power converter circuit, compare the regulated output voltage to a specified voltage threshold, and turn off the oscillator circuit when the regulated output voltage is greater than the specified threshold voltage and turn on the oscillator circuit when the regulated output voltage is less than the specified threshold voltage.

Abstract: A power gating circuit includes a first transistor to couple a power supply to a gated power rail after receiving a control signal. The power gating circuit also includes two or more transistors coupled in parallel with the first switch, the one or more transistors configured to sequentially couple the power supply to the gated power rail according to a sequence determined by a comparator circuit and one or more cascaded latches.

Abstract: A power gating circuit includes a first transistor to couple a power supply to a gated power rail after receiving a control signal. The power gating circuit also includes two or more transistors coupled in parallel with the first switch, the one or more transistors configured to sequentially couple the power supply to the gated power rail according to a sequence determined by a comparator circuit and one or more cascaded latches.

Abstract: Techniques for improving efficiency of a switched-capacitor voltage regulator are provided. In an example, a switched-capacitor voltage regulator can include a switched-capacitor network having multiple gain configurations, a clock configured to switch capacitors of the switched-capacitor network between a charge state and a discharge state to provide a scaled output voltage, and a controller configured to select a capacitor configuration associated with a gain of the multiple gain configurations to provide the scaled output voltage within a desired output voltage range while continuously switching the capacitor configuration, and to interrupt switching of the capacitor configuration to permit an output voltage of the switched-capacitor voltage regulator to fall below the scaled output voltage but to remain above a lower limit of the desired output voltage range to save power by reducing losses due to the switching.

Abstract: A switched capacitor voltage converter is provided that includes an array of switches configured to alternately switch multiple capacitors between a charge configuration in which the multiple capacitors are coupled in series with each other and in parallel with the source voltage and a discharge configuration in which a first set of capacitors having n capacitors are coupled in parallel with each other and in series with the load and a second set of capacitors having m capacitors coupled in parallel with the load.

Abstract: A switched capacitor voltage converter is provided that includes an array of switches configured to alternately switch multiple capacitors between a charge configuration in which the multiple capacitors are coupled in series with each other and in parallel with the source voltage and a discharge configuration in which a first set of capacitors having n capacitors are coupled in parallel with each other and in series with the load and a second set of capacitors having m capacitors coupled in parallel with the load.

Abstract: This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel VN level instead of the line/reference amplifier level. The pixel signal voltage VN and offset voltage VNS are read sequentially, eliminating the differential structure. Interference rejection, usually achieved by a differential signal, is obtained by using a CDS (Correlated Double Sampler) in the same way as in the prior art.

Abstract: A system and method for generating a ghost profile is disclosed. The ghost profile allows a user to use certain features in a social network without converting to a social network profile. Specifically, the ghost profiles are unsearchable and comments that originate from a ghost profile user are displayed as partial names. The ghost profile is generated when a member of the social network invites a user to join. In one example, the member is automatically added as a friend to the user's ghost profile.

Abstract: This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel VN level instead of the line/reference amplifier level. The pixel signal voltage VN and offset voltage VNS are read sequentially, eliminating the differential structure. Interference rejection, usually achieved by a differential signal, is obtained by using a CDS (Correlated Double Sampler) in the same way as in the prior art.

Abstract: The objective of this invention is to provide a solid-state image pickup device and its driving method that has a minimum circuit area and a wide dynamic range. The invention includes: a sensor array SA; a memory M; and a signal determination circuit DC. The sensor array has plural pixels in an array integrated on a semiconductor substrate. Each pixel sequentially outputs a first signal and a second signal. The memory M is connected to each column of pixels array and stores the first signal or the second signal. The signal determination circuit DC outputs signal (SS) such that it works as follows: when the first signal is input to memory M from the pixel, the signal determination circuit DC determines whether the first signal can be used. If so, the first signal is selected and the second signal is discarded and is not output to memory M. When the second signal is selected, the second signal is uploaded to memory M.

Abstract: Embodiments of the present invention may provide a power supply system that uses a capacitive voltage divider to selectively monitor various power supplies on an IC chip. The power supply system may sample a monitored power supply to a capacitor and select certain capacitors from a set of switched capacitors to divide down the sampled voltage. The resulting voltage may be compared to a voltage reference. Using different selections of switched capacitors, the monitored power supply may be compared for different voltage levels. The ratio of the sampling capacitor to the selected capacitors may determine a voltage level the comparator will trigger. Further, based on the monitored power supply level, the power supply system may turn on a switch between an external power supply and a regulated digital power supply to charge the regulated digital power supply while a main LDO is turned off.