Patents by Inventor Jose V. SANTOS Martinez

Jose V. SANTOS Martinez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12142931
    Abstract: A wireless power transmitter can include a wireless power transmitter coil adapted to magnetically couple the wireless power transmitter to a wireless power receiver, a resonant capacitor coupled to the wireless power transmitter coil to form a resonant circuit, and an inverter having an input that receives a DC voltage and an AC output coupled to the resonant circuit. The inverter can further include a plurality of switching devices coupled between the input and AC output of the inverter, a controller configured to generate pulse width modulated (PWM) drive signals for the plurality of switching devices, wherein the PWM drive signals are tri-state PWM signals having three output levels, and zero crossing detection circuitry that receives the PWM drive signals for corresponding switching devices and signals corresponding to voltages across the corresponding switching devices and generates gate drive signals for the corresponding switching devices.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: November 12, 2024
    Assignee: Apple Inc.
    Inventors: Jose V Santos Martinez, Yongxuan Hu
  • Patent number: 12047088
    Abstract: A data processing system can include a first IC including one or more A/D converters that receive analog inputs from one or more sensors and generate corresponding digital data, a second IC including one or more processing elements that operate on the digital data, and communication circuitry, coupled between the one or more A/D converters and processing elements, that includes a packetizer on the first IC that receives samples and sample data from the one or more A/D converters and assembles each sample and corresponding sample data into a packet, a primary physical interface on the first IC that communicates the packet to a secondary physical interface on the second IC, and a de-packetizer that on the second IC that receives the packet, de-packetizes it, and delivers the sample and sample data to the one or more processing elements.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: July 23, 2024
    Assignee: Apple Inc.
    Inventors: Jose V Santos Martinez, Yongxuan Hu, Nileshbhai J Shah
  • Patent number: 11764621
    Abstract: A wireless power transmitter can include an inverter that receives a DC input and generates an AC output to drive a wireless power transmit coil coupled to an output of the inverter as well as voltage and current sensors that measure the DC input. The wireless power transmitter can further include a power management accumulator including hardware that receives voltage and current samples from the voltage and current sensors and multiplies corresponding voltage and current samples to produce power samples and memory locations that store corresponding voltage, current, and power samples. The wireless power transmitter can still further include a programmable controller that controls switching devices of the inverter responsive at least in part to the voltage, current and power samples stored in the memory locations of the power management accumulator.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: September 19, 2023
    Assignee: Apple Inc.
    Inventors: Yongxuan Hu, Nileshbhai J. Shah, José V. Santos Martinez, Stephen C. Terry
  • Publication number: 20230198538
    Abstract: A data processing system can include a first IC including one or more A/D converters that receive analog inputs from one or more sensors and generate corresponding digital data, a second IC including one or more processing elements that operate on the digital data, and communication circuitry, coupled between the one or more A/D converters and processing elements, that includes a packetizer on the first IC that receives samples and sample data from the one or more A/D converters and assembles each sample and corresponding sample data into a packet, a primary physical interface on the first IC that communicates the packet to a secondary physical interface on the second IC, and a de-packetizer that on the second IC that receives the packet, de-packetizes it, and delivers the sample and sample data to the one or more processing elements.
    Type: Application
    Filed: June 1, 2022
    Publication date: June 22, 2023
    Inventors: Jose V Santos Martinez, Yongxuan Hu, Nileshbhai J Shah
  • Publication number: 20160306404
    Abstract: A circuit for limiting an in-rush current for devices coupling to a capacitive load may include a port configured to receive a device and a first capacitor coupled to the port. Additionally, the circuit may include a first resistor coupled in series with the first capacitor and a switch coupled in parallel with the first resistor. The switch is configured to close after an in-rush current event has passed, thereby bypassing the first resistor from the circuit and enabling the first capacitor to effectively filter noise from the voltage output to the port.
    Type: Application
    Filed: April 14, 2015
    Publication date: October 20, 2016
    Inventors: Jose V. SANTOS Martinez, Collin E. Connors, Yongxuan Hu