Patents by Inventor Josef E. Jedlicka

Josef E. Jedlicka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5808297
    Abstract: Semiconductor chips for use in a chip array assembly for scanning of hard-copy images include rows of photosensors, each row of photosensors having a polyimide filter layer for passing one primary color. In addition to the photosensors, a reflective area is provided on the chip, with filter portions provided on the reflective area. The filter portions are created at the same time as the filter layers placed on the photosensors. The filter layers disposed on the reflective area can be used as test sites for determining the light transmissivity of the filter layers on the photosensors.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: September 15, 1998
    Assignee: Xerox Corporation
    Inventors: Josef E. Jedlicka, Brian T. Ormond
  • Patent number: 5753959
    Abstract: Semiconductor chips, such as photosensor arrays for a full-page-width scanner or printhead chips for a full-page-width ink-jet printer, are mounted on a substrate to maintain reasonably consistent spacing among adjacent chips. To remove a defective chip from the array, the substrate is urged evenly against a work surface defining a convex bow. Alternately, back-cuts are provided along abutting edges of the chips, and the silicon around these back-cuts can be sawed away to space defective chips from neighboring good chips. By increasing the spacing of a defective chip from neighboring chips, the defective chip can be removed while minimizing the risk of damage to neighboring chips. Also, batches of chips can be originally manfactured on a single wafer as either "regular" chips or "replacement" chips, with the replacement chips being slightly shorter in a critical dimension.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: May 19, 1998
    Assignee: Xerox Corporation
    Inventors: Kraig A. Quinn, Brian T. Ormond, Josef E. Jedlicka
  • Patent number: 5696626
    Abstract: A photosensitive chip, such as used in a scanner or facsimile, defines a linear array of photosites, each photosite being covered with a filter formed from a cured translucent liquid. At the critical ends of the chip, between the end photosite in the array and the edge of the chip, there is provided a ridge which protrudes over the thickness of the filter. This ridge maintains the physical integrity of the filter.
    Type: Grant
    Filed: October 12, 1995
    Date of Patent: December 9, 1997
    Assignee: Xerox Corporation
    Inventors: Paul A. Hosier, Jagdish C. Tandon, Josef E. Jedlicka, Brian T. Ormond
  • Patent number: 5604362
    Abstract: In a photosensitive chip suitable for full-color imaging, separate photosites on the chip correspond to different primary colors in an original image. Each primary-color photosite is filtered with a polyimide doped to a particular primary color. The red-filtering layer and the blue-filtering layer are left on the non-photosensitive portions of the main surface of the chip, and together serve as a non-reflective area which prevents stray reflections from the chip. The chip is further provided with a base layer of infrared-filtering polyimide.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: February 18, 1997
    Assignee: Xerox Corporation
    Inventors: Josef E. Jedlicka, Brian T. Ormond, Debra S. Vent
  • Patent number: 5545913
    Abstract: An assembly facilitates mounting a set of abutted semiconductor chips, such as chips aligned to form a single full-page-width linear array of photosensors in a digital scanner or copier. An elongated bead of electrically conductive adhesive extends along a surface of a support substrate. A plurality of semiconductor chips is disposed along the elongated bead, each semiconductor chip including a linear array of photosensors on a front surface thereof, and a back surface attached to the support substrate by the electrically conductive adhesive. A connection block is disposed along another portion of the elongated bead, the block including a first surface contacting the bead, a second surface, and a conductor extending from the first surface to the second surface.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: August 13, 1996
    Assignee: Xerox Corporation
    Inventors: Kraig A. Quinn, Josef E. Jedlicka, Brian T. Ormond
  • Patent number: 5521125
    Abstract: A wafer design and dicing technique for creating semiconductor chips from wafers. A succession of oxide layers are deposited in first and second regions of a surface of a silicon substrate. The regions are separated by a street having no oxide layers therein, and the successive oxide layers form a vertical wall with a surface normal to the surface of the silicon substrate. A shock-absorbent material is deposited in the street, forming a concave meniscus therein. The shock-absorbent material retards the trajectories of silicon particles set into motion when the wafer is diced into chips.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: May 28, 1996
    Assignee: Xerox Corporation
    Inventors: Brian T. Ormond, Josef E. Jedlicka
  • Patent number: 5219796
    Abstract: An improved process for forming individual dies having faces that allow the dies to be assembled against other like dies to form one and/or two dimensional scanning arrays with minimal chipping and fracturing wherein the active side of a wafer is etched to form separation grooves with the wall of the grooves adjoining the die presenting a relatively wide surface to facilitate sawing, wide grooves are cut in the inactive side of the wafer opposite each separation grooves, and the wafer cut by sawing along the separation grooves, the saw being located so that the side of the saw blade facing the die is aligned with the midpoint of the wide wall so that on sawing the bottom half of the wall and the remainder of the grooves are obliterated leaving the top half of the wall to prevent cracking and chipping during sawing.
    Type: Grant
    Filed: November 4, 1991
    Date of Patent: June 15, 1993
    Assignee: Xerox Corporation
    Inventors: Kraig A. Quinn, Brian T. Ormond, Josef E. Jedlicka
  • Patent number: 5128282
    Abstract: A process for separating image sensor dies and the like from a wafer in which pairs of separation grooves separating each row of dies are formed in the active side of the wafer, with the tab between each groove pair being substantially equal to the width of the dicing blade, cutting a single bottom groove in the inactive side of the wafer opposite to and spanning each pair of separation grooves, and aligning the dicing blade with the midpoint of the wall of one groove in each pair of grooves so as to cut between the rows of dies. In a second embodiment, a two-pass separation process is enabled in which the tab between separation grooves is slightly larger than the width of the dicing blade, with the dicing blade first aligned with the midpoint of one separation groove to cut one row of dies from the wafer together with part of the tab, with the blade realigned with the midpoint of the other separate groove to cut a second row of dies and the remainder of the tab.
    Type: Grant
    Filed: November 4, 1991
    Date of Patent: July 7, 1992
    Assignee: Xerox Corporation
    Inventors: Brian T. Ormond, Kraig A. Quinn, Paul A. Hosier, Josef E. Jedlicka
  • Patent number: 5119181
    Abstract: A color chip construction especially adapted for use in fabricating full width arrays in which the individual chip photosites consisting of a blue, green, and red photodiode shaped and positioned to provide a rectangular photosite with square sides that enhance butting of the color chip with other like color chips to form full width color arrays.
    Type: Grant
    Filed: April 8, 1991
    Date of Patent: June 2, 1992
    Assignee: Xerox Corporation
    Inventors: Alain E. Perregaux, Jagdish C. Tandon, Josef E. Jedlicka, Stephen C. Corona
  • Patent number: 5031032
    Abstract: A color chip construction especially adapted for use in fabricating full width arrays in which the individual chip photosites consisting of a blue, green, and red photodiode shaped and positioned to provide a rectangular photosite with square sides that enhance butting of the color chip with other like color chips to form full width color arrays.
    Type: Grant
    Filed: March 30, 1990
    Date of Patent: July 9, 1991
    Assignee: Xerox Corporation
    Inventors: Alain E. Perregaux, Jagdish C. Tandon, Josef E. Jedlicka
  • Patent number: 4954197
    Abstract: A process for fabricating a full width array in which plural smaller chips are bonded end-to-end onto the metallic covering of an elongated substrate by an electrically conductive heat activated adhesive, in which a photocurable adhesive is used to temporarily retain the smaller chips in position while the heat activated adhesive is cured, the process accommodating the inability to cure the photocurable adhesive through the opaque chips and substrate covering by locating the photocurable adhesive so that it extends outside of the boundary of the smaller chips and forms an adhesive fillet or bridge between one side of the smaller chips and the substrate when cured by ultraviolet light.In an alternate embodiment, the photocurable adhesive is located within the boundary of the smaller chips initially but is squeezed out from below the smaller chips to form the exposed adhesive bridge when the smaller chips are placed on the substrate.
    Type: Grant
    Filed: March 30, 1989
    Date of Patent: September 4, 1990
    Assignee: Xerox Corporation
    Inventors: Josef E. Jedlicka, Ewart O. LeBlanc, Judith A. Masseth
  • Patent number: 4814296
    Abstract: A process for forming individual dies having faces that allow the dies to be assembled against other like dies to form one and/or two dimensional scanning arrays wherein the active side of a wafer is etched to form small V-shaped grooves defining the die faces, relatively wide grooves are cut in the inactive side of the wafer opposite each V-shaped groove, and the wafer cut by sawing along the V-shaped grooves, the saw being located so that the side of the saw blade facing the die is aligned with the bottom of the V-shaped groove so that there is retained intact one side of the V-shaped groove to intercept and prevent cracks and chipping caused by sawing from damaging the die active surface and any circuits thereon.
    Type: Grant
    Filed: August 28, 1987
    Date of Patent: March 21, 1989
    Assignee: Xerox Corporation
    Inventors: Josef E. Jedlicka, Kimberly R. Page, Alain E. Perregaux, Fred F. Wilczak, Jr.
  • Patent number: 4641949
    Abstract: The present invention is concerned with a switching element comprised of oppositely disposed conductive fiber brushes and/or brush-like elements for detecting the presence or absence of paper at various locations in a xerographic copy machine. The oppositely disposed brushes are made from poly-acrylo-nitrile, a carbon based polymer material, which can be fabricated with relatively low values of resistance. Typical fiber bundles may consist of 6000 individual fibers each of 6-10 microns in diameter. In operation each individual conductive fiber acts as a separate electrical path through which the external circuit is completed. Passage of paper through the "nip" of the fiber to fiber electrical contact opens the circuit which is easily detected through associated circuitry which indicates the presence of paper. Likewise, arrays incorporating multiple such sensor switches may be fabricated for the purpose of indicating the size of the document interrupting specific low resistance fiber-fiber switches.
    Type: Grant
    Filed: August 26, 1985
    Date of Patent: February 10, 1987
    Assignee: Xerox Corporation
    Inventors: Stanley J. Wallace, Josef E. Jedlicka, Wilbur M. Peck, Jr.