Patents by Inventor Josef Hoeglauer

Josef Hoeglauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190148332
    Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Applicant: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Thorsten Meyer, Xaver Schloegel, Thomas Behrens, Josef Hoeglauer
  • Publication number: 20190081562
    Abstract: A power semiconductor system includes a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board, and an inductor module attached to the power stage module and having an inductor electrically connected to an output node of the power stage module. The inductor is formed from a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Corresponding methods of manufacturing the power semiconductor system and the inductor module are also disclosed.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Publication number: 20190080980
    Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; a top layer arranged at the package top side and electrically connected with the second load terminal; and a heat spreader arranged external of the package body and in electrical contact with the top layer. A top surface of the heat spreader has an area greater than the area of the bottom surface.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 14, 2019
    Inventors: Ralf Otremba, Markus Dinkel, Ulrich Froehler, Josef Hoeglauer, Uwe Kirchner, Guenther Lohmann, Klaus Schiess, Xaver Schloegel
  • Patent number: 10224912
    Abstract: A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: March 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Gerhard Noebauer
  • Patent number: 10204845
    Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Amirul Afiq Hud, Chooi Mei Chong, Josef Hoeglauer, Klaus Schiess, Lee Shuang Wang, Matthias Strassburg, Teck Sim Lee, Xaver Schloegel
  • Patent number: 10109609
    Abstract: A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including Pb, and an electrically conductive member arranged on the second layer.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 23, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Publication number: 20180301398
    Abstract: A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal, The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.
    Type: Application
    Filed: April 16, 2018
    Publication date: October 18, 2018
    Inventors: Ralf Otremba, Chooi Mei Chong, Markus Dinkel, Josef Hoeglauer, Klaus Schiess, Xaver Schloegel
  • Publication number: 20180158758
    Abstract: A method of manufacturing a hybrid leadframe is provided comprising providing a thin leadframe layer comprising a diepad and a structured region and attaching a metal layer on the diepad, wherein the metal layer has a thickness which is larger than a thickness of the thin leadframe layer.
    Type: Application
    Filed: February 6, 2018
    Publication date: June 7, 2018
    Inventors: Ralf OTREMBA, Chooi Mei Chong, Josef Hoeglauer, Teck Sim Lee, Klaus Schiess, Xaver Schloegel
  • Patent number: 9991183
    Abstract: A semiconductor component includes an inner semiconductor component housing and an outer semiconductor component housing. The inner semiconductor component housing includes a semiconductor chip, a first plastic housing composition and first housing contact surfaces. At least side faces of the semiconductor chip are embedded in the first plastic housing composition and the first housing contact surfaces are free of the first plastic housing composition and include a first arrangement. The outer semiconductor component housing includes a second plastic housing composition and second housing contact surfaces which include a second arrangement. The inner semiconductor component housing is situated within the outer semiconductor component housing and is embedded in the second plastic housing composition. At least one of the first housing contact surfaces is electrically connected with at least one of the second housing contact surfaces.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: June 5, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Josef Hoeglauer, Teck Sim Lee, Ralf Otremba, Klaus Schiess, Xaver Schloegel, Juergen Schredl
  • Publication number: 20180061745
    Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.
    Type: Application
    Filed: August 28, 2017
    Publication date: March 1, 2018
    Inventors: Ralf Otremba, Amirul Afiq Hud, Chooi Mei Chong, Josef Hoeglauer, Klaus Schiess, Lee Shuang Wang, Matthias Strassburg, Teck Sim Lee, Xaver Schloegel
  • Patent number: 9824958
    Abstract: Various embodiments provide a chip carrier structure. The chip carrier structure may include a structured metallic chip carrier; encapsulating material at least partially filling the structure; wherein the main surfaces of the metallic chip carrier are free from the encapsulating material.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: November 21, 2017
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess
  • Patent number: 9806029
    Abstract: An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, and a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: October 31, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Chooi Mei Chong
  • Patent number: 9786584
    Abstract: Representative implementations of devices and techniques provide isolation between a carrier and a component mounted to the carrier. A multi-layer device having lateral elements provides electrical isolation at a preset isolation voltage while maintaining a preselected thermal conductivity between the component and the carrier.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: October 10, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess
  • Publication number: 20170288654
    Abstract: A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.
    Type: Application
    Filed: April 3, 2017
    Publication date: October 5, 2017
    Inventors: Ralf Otremba, Josef Hoeglauer, Gerhard Noebauer
  • Patent number: 9627292
    Abstract: A semiconductor housing includes a fixing mechanism and at least one side having structurings. A method for producing a semiconductor device is provided in which a thermally conductive paste is applied on the at least one side of the semiconductor housing and/or of a heat sink. The semiconductor housing is fixed to the heat sink by means of the fixing mechanism. A pressure is exerted on the thermally conductive paste by means of the fixing mechanism and the thermally conductive paste is diverted by means of diversion channels depending on the pressure exerted.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: April 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Juergen Schredl
  • Publication number: 20170047315
    Abstract: A method of manufacturing a semiconductor device includes mounting a first semiconductor power chip on a first carrier, mounting a second semiconductor power chip on a second carrier, bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip, and mounting a third semiconductor chip over the contact clip.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Chooi Mei Chong
  • Patent number: 9515060
    Abstract: A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip. A semiconductor logic chip is mounted over the contact clip.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: December 6, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Chooi Mei Chong
  • Publication number: 20160315033
    Abstract: A device includes a logic semiconductor chip having a contact electrode. The contact electrode is configured to be electrically coupled to a contact clip based on a clip bonding technique.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 27, 2016
    Inventors: Ralf Otremba, Josef Hoeglauer, Aliaksandr Subotski
  • Patent number: 9449902
    Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: September 20, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess
  • Patent number: 9437516
    Abstract: A semiconductor package includes a semiconductor die and a metal clip. In one embodiment, the semiconductor die is embedded in an insulating material and has a first surface facing in a first direction, a second surface facing in a second direction opposite the first direction and an edge extending between the first and second surfaces. The metal clip is embedded in the insulating material above the die and bonded to the second surface of the die. Part of the metal clip extends laterally beyond the edge of the die and vertically in the first direction to provide galvanic redistribution at the second surface of the die. Other embodiments of semiconductor packages are also provided.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: September 6, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Höglauer, Manfred Schindler, Johannes Lodermeyer, Thorsten Scharf