Patents by Inventor Josef Hoeglauer

Josef Hoeglauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electronic Device and Method for Fabricating an Electronic Device
    Publication number: 20150214133
    Abstract: An electronic device includes a semiconductor chip including an electrode, a substrate element and a contact element connecting the electrode to the substrate element. The electronic device further includes an encapsulant configured to leave the contact element at least partially exposed such that a heatsink may be connected to the contact element.
    Type: Application
    Filed: January 28, 2014
    Publication date: July 30, 2015
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Teck Sim Lee, Xaver Schloegel, Klaus Schiess
  • Connection Structure and Electronic Component
    Publication number: 20150200178
    Abstract: A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including Pb, and an electrically conductive member arranged on the second layer.
    Type: Application
    Filed: January 13, 2014
    Publication date: July 16, 2015
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Semiconductor Packaging Arrangement
    Publication number: 20150194373
    Abstract: A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 9, 2015
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Chip-Embedded Packages with Backside Die Connection
    Publication number: 20150194362
    Abstract: A semiconductor package includes a semiconductor die and a metal clip. In one embodiment, the semiconductor die is embedded in an insulating material and has a first surface facing in a first direction, a second surface facing in a second direction opposite the first direction and an edge extending between the first and second surfaces. The metal clip is embedded in the insulating material above the die and bonded to the second surface of the die. Part of the metal clip extends laterally beyond the edge of the die and vertically in the first direction to provide galvanic redistribution at the second surface of the die. Other embodiments of semiconductor packages are also provided.
    Type: Application
    Filed: January 7, 2014
    Publication date: July 9, 2015
    Inventors: Ralf Otremba, Josef Höglauer, Manfred Schindler, Johannes Lodermeyer, Thorsten Scharf
  • SWITCHED-MODE POWER CONVERTER WITH SPLIT PARTITIONING
    Publication number: 20150171748
    Abstract: A power converter is described that includes components arranged within a first die and a second die of a single package. The first die includes one or more first switches coupled to a switching node of a power stage. The second die includes one or more second switches coupled to the switching node of the power stage, a feedback control unit configured to detect a current level at the one or more second switches of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the current level detected by the feedback control unit.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 18, 2015
    Applicant: Infineon Technologies Austria AG
    Inventors: Christoph Sandner, Roman Riederer, Josef Höglauer, Stephan Auer
  • Semiconductor device
    Patent number: 9059083
    Abstract: A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: June 16, 2015
    Assignee: Infineon Technologies AG
    Inventors: Henrik Ewe, Joachim Mahler, Manfred Mengel, Reimund Engl, Josef Hoeglauer, Jochen Dangelmaier
  • Chip package and method for manufacturing the same
    Patent number: 9059155
    Abstract: Various embodiments provide a chip package. The chip package may include a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip carrier; and a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 16, 2015
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Henrik Ewe, Anton Prueckl, Joachim Mahler, Frank Daeche, Josef Hoeglauer, Riccardo Pittassi
  • Electronic Device
    Publication number: 20150162287
    Abstract: An electronic device includes multiple semiconductor chips in a single housing. Such semiconductor chips may comprise different semiconductor materials, for example they may comprise GaN. Using bonding clips instead of bonding wires is an efficient way of connecting such semiconductor chips to a substrate.
    Type: Application
    Filed: December 6, 2013
    Publication date: June 11, 2015
    Inventors: Khalil Hosseini, Joachim Mahler, Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess
  • Multi-die package with separate inter-die interconnects
    Patent number: 9054040
    Abstract: A first electrode at a first side of a first semiconductor die is connected to a first conductive region of a substrate. A first electrode at a first side of a second semiconductor die is connected to a second conductive region of the substrate. Each die has a second electrode at an opposing second side of the respective die. A first metal layer extends from a periphery region of the substrate to over the first die. The first metal layer has a generally rectangular cross-sectional area and connects one of the conductive regions in the periphery region of the substrate to the second electrode of the first die. A second metal layer separate from the first metal layer extends over the first and second dies. The second metal layer has a generally rectangular cross-sectional area and connects the second electrodes of the first and second dies.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: June 9, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Khalil Hosseini, Joachim Mahler, Josef Höglauer
  • Device Including Two Power Semiconductor Chips and Manufacturing Thereof
    Publication number: 20150155271
    Abstract: A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.
    Type: Application
    Filed: February 9, 2015
    Publication date: June 4, 2015
    Inventors: Ralf Otremba, Josef Hoeglauer, Joachim Mahler, Johannes Lodermeyer
  • Multi-level semiconductor package
    Patent number: 9041170
    Abstract: A semiconductor package includes a semiconductor die having a first electrode at a first side and a second electrode at a second side opposing the first side, a first lead under the semiconductor die and connected to the first electrode at a first level of the package, and a second lead having a height greater than the first lead and terminating at a second level in the package above the first level, the second level corresponding to a height of the semiconductor die. A connector of a single continuous planar construction over the semiconductor die and the second lead is connected to both the second electrode and the second lead at the same second level of the package.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Höglauer, Klaus Schiess, Chooi Mei Chong
  • Packaged device comprising non-integer lead pitches and method of manufacturing the same
    Patent number: 9035437
    Abstract: Packaged chips comprising non-integer lead pitches, systems and methods for manufacturing packaged chips are disclosed. In one embodiment a packaged device includes a first chip, a package encapsulating the first chip and a plurality of leads protruding from the package, wherein the plurality of leads comprises differing non-integer multiple lead pitches.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 19, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Guenther Lohmann, Josef Hoeglauer, Teck Sim Lee, Matteo-Alessandro Kutschak, Wolfgang Peinhopf
  • Semiconductor device having a clip contact
    Patent number: 9018744
    Abstract: A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: April 28, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Khalil Hosseini
  • Transistor arrangement with semiconductor chips between two substrates
    Publication number: 20150092375
    Abstract: An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, and a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 2, 2015
    Applicant: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Chooi Mei Chong
  • Electronic Component, Arrangement and Method
    Publication number: 20150091176
    Abstract: An electronic component includes at least one semiconductor device and a redistribution board comprising at least two nonconductive layers and a conductive redistribution structure. The semiconductor device is embedded in the redistribution board and electrically coupled to the redistribution structure and the redistribution board has a side face with a step. An outer contact pad of the redistribution structure is arranged on the step.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Chip module and a method for manufacturing a chip module
    Patent number: 8987880
    Abstract: In various embodiments, a chip module may include a first chip; and a leadframe with a first leadframe area and a second leadframe area, wherein the first leadframe area is electrically insulated from the second leadframe area; wherein the first chip is arranged at least partially on the first leadframe area and at least partially on the second leadframe area.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Josef Hoeglauer, Ralf Otremba, Xaver Schloegel
  • Semiconductor device using diffusion soldering
    Patent number: 8975117
    Abstract: A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Fong Lim, Abdul Rahman Mohamed, Chooi Mei Chong, Ida Fischbach, Xaver Schloegel, Juergen Schredl, Josef Hoeglauer
  • Device including two power semiconductor chips and manufacturing thereof
    Patent number: 8975711
    Abstract: A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Joachim Mahler, Johannes Lodermeyer
  • Redistribution board, electronic component and module
    Patent number: 8975735
    Abstract: A redistribution board includes a first conductive layer including a redistribution structure for low voltage signals, a second conductive layer including a redistribution structure for high voltage signals, and a non-conductive layer. The second conductive layer is spaced apart from the first conductive layer by the non-conductive layer. The redistribution board further includes a conductive connector extending from a mounting surface of the redistribution board to the second conductive layer. The conductive connector is surrounded by a low voltage trace of the first conductive layer.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Höglauer
  • Semiconductor Packages Having Multiple Lead Frames and Methods of Formation Thereof
    Publication number: 20150060878
    Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.
    Type: Application
    Filed: November 6, 2014
    Publication date: March 5, 2015
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess