Abstract: A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.

Abstract: Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.

Abstract: A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

Abstract: A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.

Abstract: An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.

Abstract: An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.

Abstract: A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.

Abstract: A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.

Abstract: A method of analyzing and designing circuits comprising creating a set of interpolated models for transistor devices; creating a set of characterized (direct fit) models for the transistor devices; analyzing the transistor devices within a netlist for matches in the set of characterized models; and providing a choice of using the matched characterized models or one of the interpolated models in designing the circuits.

Abstract: A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

Abstract: A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.

Abstract: An integrated circuit, comprising: a predefined block of functional circuitry having a plurality of I/O pins; and a backside I/O pad electrically connected to each I/O pin through a backside via of the integrated circuit.

Abstract: A method of analyzing and designing circuits comprising creating a set of interpolated models for transistor devices; creating a set of characterized (direct fit) models for the transistor devices; analyzing the transistor devices within a netlist for matches in the set of characterized models; and providing a choice of using the matched characterized models or one of the interpolated models in designing the circuits.

Abstract: A voltage regulated power supply test circuit including: a voltage regulator electrically connected to at least one regulated voltage node of a functional circuit of an integrated circuit chip; and means for selectively connecting between one of the at least one regulated voltage nodes and ground with at least one load circuit adapted to put an emulated current load of the functional circuit on the regulated voltage supply.

Abstract: A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.

Abstract: A re-centering system (116) for re-centering the control parameter of a phase lock loop (PLL) (112). The re-centering system includes sources (140) for obtaining/storing operating parameters, such as environmental data (184), setup data (188), and other knowns data (192). At least one state machine (132) utilizes the operating parameters to adjust the topology of the PLL so as to achieve a desirable topology for each target output frequency (18) that substantially centers the performance envelope(s) (120, 124, 128) to a desired pre-selected value of the control parameter. The re-centering system also includes a comparator (136) for comparing measured values of the control parameter to a pre-selected value. The state machine utilizes the output of the comparator to substantially center the corresponding performance envelope at the pre-selected value.

Abstract: A voltage regulated power supply test circuit including: a voltage regulator electrically connected to at least one regulated voltage node of a functional circuit of an integrated circuit chip; and means for selectively connecting between one of the at least one regulated voltage nodes and ground with at least one load circuit adapted to put an emulated current load of the functional circuit on the regulated voltage supply.

Abstract: A re-centering system (116) for re-centering the control parameter of a phase lock loop (PLL) (112). The re-centering system includes sources (140) for obtaining/storing operating parameters, such as environmental data (184), setup data (188), and other knowns data (192). At least one state machine (132) utilizes the operating parameters to adjust the topology of the PLL so as to achieve a desirable topology for each target output frequency (18) that substantially centers the performance envelope(s) (120, 124, 128) to a desired pre-selected value of the control parameter. The re-centering system also includes a comparator (136) for comparing measured values of the control parameter to a pre-selected value. The state machine utilizes the output of the comparator to substantially center the corresponding performance envelope at the pre-selected value.

Abstract: A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.

Abstract: A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.