Abstract: A method of testing a digital logic circuit comprises first providing a logic circuit having a plurality of interconnected circuits each having an input and an output; determining a gate level representation of the logic circuit including test nets for determining faults in the circuit; and identifying a portion of the nets which are most difficult to test, including nets which are most difficult to control and nets which are most difficult to observe. The method then includes inserting into the logic circuit control latches for nets which are determined to be most difficult to control and inserting into the logic circuit observation latches for nets which are determined to be most difficult to observe. Using the inserted control latches and observation latches, the method further includes testing the nets which are determined to be most difficult to control and nets which are hardest to observe and determining faults in the circuit.

Abstract: The present invention provides a transceiver for receiving and transmitting data over a network, and a method for testing the same. In particular, the present invention provides a physical layer transceiver having a built-in-self-test (BIST) device that allows for, among other things, pulse density/width variation and jitter control.

Abstract: An integrated circuit, comprising: a predefined block of functional circuitry having a plurality of I/O pins; and a backside I/O pad electrically connected to each I/O pin through a backside via of the integrated circuit.

Abstract: The present invention provides a receiver device having multiple voltage supplies that allows the output stage of the receiver device to go to a safe state whenever its voltage is disconnected or powered-down, independent of any of its normal control circuits. Furthermore, the isolation of the multiple voltage supplies provides a low skew at the output of the receiver device.

Abstract: The present invention provides a receiver device having multiple voltage supplies that allows the output stage of the receiver device to go to a safe state whenever its voltage is disconnected or powered-down, independent of any of its normal control circuits. Furthermore, the isolation of the multiple voltage supplies provides a low skew at the output of the receiver device.

Abstract: A system and method are described for separating the bulk connections for FETs on a semiconductor wafer from the supply rails, testing the wafer to determine if a shift in the threshold voltage, VT, of certain devices within the wafer, as defined by the bulk-wells, can remove an AC defect in the IC circuit, and tailoring the voltage or voltages applied to the bulk nodes, post-manufacture, such that the integrated circuit meets its performance targets or is sorted to a more valuable performance level. The method requires generating a gate level netlist of the IC's circuitry and performing timing calculations on these circuit netlists using static timing analyses, functional delay simulations, circuit activity analyses, and functional performance testing. The failures are then correlated to respective IC circuits, worst case slack circuits are investigated, and proposed changes to the threshold voltages are employed in the hardware.

Abstract: A highly flexible system for performing a bitwrite operation on each bit of a Field Programmable Memory Array, while maintaining low-level routing requirements. The system consists of a bitwrite control subarray which is equal in width to the number of memory cells per word of a Field Programmable Memory Array and equal in height to 2N where N is the number chosen decode variations. Each cell of a Field Programmable Memory Array is associated via a bitwrite line with one cell of the bitwrite control subarray so that each cell can be independently controlled. The bitwrite control subarray can be programmed via a data bus prior to functional operation of the Field Programmable Memory Array, or while functional operation in the array continues.

Abstract: A system and method for testing the most complex portions of transceiver devices integrated into digital VLSI chips. The testing is performed in a manufacturing environment with minimal external hardware and using a combination of test-specific circuitry and pattern algorithms built into a mixed signal transceiver implementing a test methodology suitable for application and measurement on a digital tester.

Abstract: Apparatus and methods for cross-coupling bitline segments in a memory array are provided. Bitline segments, each having a plurality of drive circuits and output circuits connected thereto, are cross-coupled such that the states of a first bitline segment can be transmitted to another bitline segment. The segments are conductively isolated such that their resistance-capacitance characteristics can be controlled while providing bi-directional data transfer along the entire length of the segmented bitline. Embodiments are also disclosed that support cross-coupling of bitline segments which are operated using pre-charge/discharge techniques.

Abstract: A programmable interconnection system for a programmable array includes pluralities of parallel buses for rows and columns of logic cells arranged in the array. Two groups of seven buses are provided for each row or column of logic cells. The buses include conductors connectable to each other, and selectively connectable to, or isolated from, the logic cells. A hierarchy of conductor lengths is disclosed to provide intra-sector and inter-sector bussing. Staggered switching is employed for adjacent sector access.

Abstract: A process tolerant delay circuit includes a plurality of inverters that receive an input signal and provide an output signal related to the input signal but including a propagation delay of the plurality of inverters. At least one inverter comprises FETs of minimum channel lengths dependent upon a fabrication process by which the circuit was made. Accordingly, the plurality of inverters have a propagation delay dependent upon the fabrication process. A delay compensation device receives the output signal of the inverters and provides a compensated output signal related to the received signal but including a variable delay established in accordance with a control signal. A process sense stack provides the control signal only during a transition of the input signal, and with a value dependent upon a channel length of a FET device thereof.