Patents by Inventor Joseph D. Cuchiaro
Joseph D. Cuchiaro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6285048Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 2000 Å. Typical gain sizes are 40 nanometers and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and an xylene exchange is preformed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 675° C. and 850° C.Type: GrantFiled: December 10, 1993Date of Patent: September 4, 2001Assignees: Symetrix Corporation, Matsushita Electronics CorporationInventors: Masamichi Azuma, Michael C. Scott, Carlos A. Paz de Araujo, Joseph D. Cuchiaro
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Patent number: 6281534Abstract: A liquid precursor for forming a thin film of ferroelectric metal oxide in an integrated circuit contains metal oxides in excess of the stoichiometrically balanced amount. When the precursor comprises strontium, bismuth, tantalum and niobium for forming strontium bismuth tantalum niobate, the precursor contains excess amounts of at least one of tantalum and niobium. Capacitors containing thin films of layered superlattice material made from a precursor containing excess tantalum and niobium show good polarizability and low percentage imprint after 1010 negative polarization switching pulses at 75° C., and after 109 negative polarization switching pulses at 125° C.Type: GrantFiled: October 13, 1998Date of Patent: August 28, 2001Assignees: Symetrix Corporation, Matsushita Electronics CorporationInventors: Koji Arita, Shinichiro Hayashi, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
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Publication number: 20010013614Abstract: A diffusion barrier layer in an integrated circuit is located to inhibit undesired diffusion of chemical species from local interconnects into layered superlattice material in a thin film memory capacitor. The diffusion barrier layer comprises iridium oxide. The thin film of layered superlattice material is ferroelectric or nonferroelectric, high-dielectric constant material. Preferably, the thin film comprises ferroelectric layered superlattice material. The diffusion barrier layer is located between a local interconnect and the memory capacitor. Preferably, the diffusion barrier layer is in direct contact with the local interconnect. The iridium-oxide diffusion barrier is effective for preventing diffusion of metals, silicon and other chemical species.Type: ApplicationFiled: January 24, 2001Publication date: August 16, 2001Inventors: Vikram Joshi, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
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Publication number: 20010012698Abstract: A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulas AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1−x)(TayNb1−y)2O6, where 0≦x≦1.0 and 0≦y≦1.0; (BaxSr1−x)2(TayNb1−y)2O7, where 0≦x≦1.0 and 0≦y≦1.0; and (BaxSr1−x)2Bi2(TayNby−1)2O10, where 0≦x≦1.0 and 0≦y≦1.0. Thin films according to the invention have a relative dielectric constant ≧40, and preferably about 100.Type: ApplicationFiled: March 2, 2001Publication date: August 9, 2001Applicant: Symetrix CorporationInventors: Shinichiro Hayashi, Vikram Joshi, Narayan Solayappan, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
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Publication number: 20010010377Abstract: A hydrogen barrier layer is formed above a ferroelectric thin film in an integrated circuit. The hydrogen barrier layer is directly over a protected segment of the ferroelectric thin film, while a sacrificial segment of the ferroelectric thin film extends laterally beyond the edges of the hydrogen barrier layer. The sacrificial segment absorbs hydrogen so that it cannot diffuse laterally into the protected segment of the ferroelectric thin film. After it absorbs hydrogen, the sacrificial segment is etched away to allow electrical connection to circuit layers below it. The ferroelectric thin film preferably comprises a layered superlattice compound. Excess bismuth or niobium added to the standard precursor solution of a strontium bismuth tantalum niobate compound helps to reduce hydrogen degradation of the ferroelectric properties.Type: ApplicationFiled: February 7, 2001Publication date: August 2, 2001Applicant: Symetrix Corporation and NEC CorporationInventors: Joseph D. Cuchiaro, Akira Furuya, Carlos A. Paz de Araujo, Yoichi Miyasaka
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Patent number: 6225156Abstract: A hydrogen barrier layer is formed above a ferroelectric thin film in an integrated circuit. The hydrogen barrier layer is directly over a protected segment of the ferroelectric thin film, while a sacrificial segment of the ferroelectric thin film extends laterally beyond the edges of the hydrogen barrier layer. The sacrificial segment absorbs hydrogen so that it cannot diffuse laterally into the protected segment of the ferroelectric thin film. After it absorbs hydrogen, the sacrificial segment is etched away to allow electrical connection to circuit layers below it. The ferroelectric thin film preferably comprises a layered superlattice compound. Excess bismuth or niobium added to the standard precursor solution of a strontium bismuth tantalum niobate compound helps to reduce hydrogen degradation of the ferroelectric properties.Type: GrantFiled: April 17, 1998Date of Patent: May 1, 2001Assignees: Symetrix Corporation, NEC CorporationInventors: Joseph D. Cuchiaro, Akira Furuya, Carlos A. Paz de Araujo, Yoichi Miyasaka
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Patent number: 6225656Abstract: A protective layer in a ferroelectric integrated circuit contains small amounts of oxygen to protect ferroelectric oxide material against hydrogen degradation during the fabrication process. Typically, the protective layer is a hydrogen diffusion barrier layer formed to cover a thin film of ferroelectric oxide material. In one method, a small amount of oxygen is included in the sputter atmosphere during deposition of a hydrogen diffusion barrier or a metallized wiring layer. The oxygen forms oxides that inhibit diffusion of hydrogen towards the ferroelectric oxide material. The oxygen forms a concentration gradient so that the oxygen concentration in the interior of the protective layer is zero, and the oxygen concentration near the surfaces of the layer is about two weight percent.Type: GrantFiled: December 1, 1998Date of Patent: May 1, 2001Assignees: Symetrix Corporation, NEC CorporationInventors: Joseph D. Cuchiaro, Akira Furuya, Carlos A. Paz de Araujo, Yoichi Miyasaka
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Patent number: 6207465Abstract: In a ferroelectric integrated circuit, a hydrogen barrier layer comprising titanium or titanium nitride or both is formed over a metal oxide element to protect it from hydrogen degradation. After hydrogen annealing and other process steps causing hydrogenating or reducing conditions, the hydrogen barrier layer is removed in a two-step etching process. The first etch step is a dry etch, preferably a standard ion-mill etching process, which rapidly removes most of the hydrogen barrier layer. The second step is a wet, chemical etch, preferably using a solution containing NH4OH, H2O2, and H2O, which selectively removes remnants of the hydrogen barrier layer from the circuit by oxidizing a chemical element of the barrier layer. The metal oxide material preferably comprises a layered superlattice compound.Type: GrantFiled: April 17, 1998Date of Patent: March 27, 2001Assignees: Symetrix Corporation, NEC CorporationInventors: Joseph D. Cuchiaro, Akira Furuya, Carlos A. Paz de Araujo, Yoichi Miyasaka
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Patent number: 6198225Abstract: A thin film of ferroelectric layered superlattice material in a flat panel display device is energized to selectively influence the display image. In one embodiment, a voltage pulse causes the layered superlattice material to emit electrons that impinge upon a phosphor, causing the phosphor to emit light. In another embodiment, an electric potential creates a remanent polarization in the layered superlattice material, which exerts an electric field in liquid crystal layer, thereby influencing the transmissivity of light through the liquid crystal. The layered superlattice material is a metal oxide formed using an inventive liquid precursor containing an alkoxycarboxylate. The thin film thickness is preferably in the range 50-140 nm, so that polarizabilty and transparency of the thin film is enhanced. A display element may comprise a varistor device to prevent cross-talk between pixels and to enable sudden polarization switching. A functional gradient in the ferroelectric thin film enhances electron emission.Type: GrantFiled: June 7, 1999Date of Patent: March 6, 2001Assignees: Symetrix Corporation, Matsushita Electronics CorporationInventors: Gota Kano, Yasuhiro Shimada, Shinichiro Hayashi, Koji Arita, Carlos A. Paz de Araujo, Joseph D. Cuchiaro, Larry D. McMillan
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Patent number: 6174213Abstract: Metal organic precursor compounds are dissolved in an organic solvent to form a nonaqueous liquid precursor. The liquid precursor is applied to the inner envelope surface of a fluorescent lamp and heated to form a metal oxide thin film layer. The metal oxide thin film layer may be a conductor, a protective layer or provide other functions. The films have a thickness of from 20 nm to 500 nm. A conductive layer comprising tin-antimony oxide with niobium dopant may be fabricated to have a differential resistivity profile by selecting a combination of precursor composition and annealing temperatures.Type: GrantFiled: September 1, 1999Date of Patent: January 16, 2001Assignees: Symetrix Corporation, Matsushita Electronics CorporationInventors: Carlos A. Paz de Araujo, Jolanta Celinska, Joseph D. Cuchiaro, Jeffrey W. Bacon, Larry D. McMillan, Akihiro Matsuda, Gota Kano, Yoshio Yamaguchi, Tatsuo Morita, Hideo Nagai
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Patent number: 6165802Abstract: An integrated circuit is formed that contains a ferroelectric element comprising metal oxide material containing at least two metals. An oxygen-recovery anneal is conducted in ambient oxygen at a temperature range from 300.degree. to 1000.degree. C. for a time period from 20 minutes to 2 hours. The oxygen-recovery anneal reverses the effects of hydrogen degradation and restores ferroelectric properties. The oxygen-recovery anneal is more effective as the annealing temperature and annealing time increase. Preferably the metal oxide element comprises a layered superlattice compound. Hydrogen degradation of the ferroelectric properties is minimized when the layered superlattice compound comprises strontium bismuth tantalum niobate and the niobium/tantalum mole ratio in the precursor is about 0.4.Type: GrantFiled: April 17, 1998Date of Patent: December 26, 2000Assignees: Symetrix Corporation, NEC CorporationInventors: Joseph D. Cuchiaro, Akira Furuya, Carlos A. Paz de Araujo, Yoichi Miyasaka
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Patent number: 6130103Abstract: An integrated circuit is formed that contains a ferroelectric element comprising metal oxide material containing at least two metals. Various methods and structures are applied to minimize the degradation of ferroelectric properties caused by hydrogen during fabrication of the circuit. Oxygen is added to the some elements of the integrated circuit to serve as a getter of hydrogen during fabrication steps. To minimize hydrogen degradation, the ferroelectric compound can be fabricated from a liquid precursor containing one or more of the constituent metals in excess of the amount corresponding to a stoichiometrically balanced concentration. A hydrogen barrier layer, preferably comprising titanium nitride, is formed to cover the top of the ferroelectric element. A hydrogen heat treatment in hydrogen gas is performed on the integrated circuit at a temperature from 200.degree. to 350.degree. C.Type: GrantFiled: April 17, 1998Date of Patent: October 10, 2000Assignees: Symetrix Corporation, NEC CorporationInventors: Joseph D. Cuchiaro, Akira Furuya, Carlos A. Paz de Araujo, Yoichi Miyasaka
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Patent number: 6080592Abstract: An integrated curcuit includes a layered superlattice material having the .sub.formula A1w1.sup.+a1 A2.sub.w2.sup.+a2 . . . Aj.sub.wj.sup.+aj S1.sub.x1.sup.+s1 S2.sub.x2.sup.+s2 . . . Sk.sub.xk.sup.+sk B1.sub.y1.sup.+b1 B2.sub.y2.sup.+b2 . . . Bl.sub.yl.sup.+bl Q.sub.z.sup.-2, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . Bl represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in non-volatile memories. Others are high dielectric constant materials that do not degrade or breakdown over long periods of use and are applied in volatile memories.Type: GrantFiled: June 7, 1995Date of Patent: June 27, 2000Assignee: Symetrix CorporationInventors: Carlos A. Paz de Araujo, Joseph D. Cuchiaro, Michael C. Scott, Larry D. McMillan
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Patent number: 6056994Abstract: A precursor liquid comprising several metal 2-ethylhexanoates, such as strontium, tantalum, and bismuth 2-ethylhexanoates, in a xylenes/methyl ethyl ketone solvent is prepared, and deposited on a substrate. In one embodiement the substrate is placed within a vacuum deposition chamber, the precursor liquid is misted, and the mist is flowed into the deposition chamber while maintaining the chamber at ambient temperature to deposit the precursor liquid on the substrate. In another embodiment, the precursor is spin-coated on the substrate. The liquid is dried, baked, and annealed to form a thin film of a layered superlattice material, such as strontium bismuth tantalate, on the substrate.Type: GrantFiled: June 7, 1995Date of Patent: May 2, 2000Assignee: Symetrix CorporationInventors: Carlos A. Paz de Araujo, Larry D. McMillan, Michael C. Scott, Joseph D. Cuchiaro
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Patent number: 6051858Abstract: A transistor on a silicon substrate is covered by an insulating layer. A conducting plug passes through the insulating layer to the transistor drain. The bottom electrode of a ferroelectric capacitor that directly overlies the plug and drain contacts the plug. The ferroelectric layer is self-patterned and completely overlies the memory cell. A self-patterned sacrificial layer completely overlies the ferroelectric layer. The bottom electrode of the capacitor is completely enclosed by the ferroelectric layer, the insulating layer, and the conducting plug.Type: GrantFiled: July 15, 1997Date of Patent: April 18, 2000Assignees: Symetrix Corporation, Mitsubishi Materials CorporationInventors: Hiroto Uchida, Nobuyuki Soyama, Katsumi Ogi, Michael C. Scott, Joseph D. Cuchiaro, Larry D. McMillan, Carlos A. Paz de Araujo
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Patent number: 6022669Abstract: A first photosensitive liquid solution is applied to a substrate, patterned through exposure to radiation and development, and annealed to form a desired solid material, such as SrBi.sub.2 Ta.sub.2 O.sub.9, that is incorporated into a component of an integrated circuit Fabrication processes are designed protect the self-patterned solid material from conventional IC processing and to protect the conventional materials, such as silicon, from elements in the self-patterned solid material. In one embodiment, a layer of bismuth oxide is formed on the SrBi.sub.2 Ta.sub.2 O.sub.9 and a silicon oxide hole is etched to the bismuth oxide. The bismuth oxide protects the SrBi.sub.2 Ta.sub.2 O.sub.9 from the etchant, and is reduced by the etchant to bismuth. Any remaining bismuth oxide and much of the bismuth are vaporized in the anneal, and the remaining bismuth is incorporated into the SrBi.sub.2 Ta.sub.2 O.sub.9.Type: GrantFiled: July 26, 1996Date of Patent: February 8, 2000Assignees: Symetrix Corporation, Mitsubishi Materials CorporationInventors: Hiroto Uchida, Nobuyuki Soyama, Kensuke Kageyama, Katsumi Ogi, Michael C. Scott, Joseph D. Cuchiaro, Gary F. Derbenuick, Larry D. McMillan, Carlos A. Paz de Araujo
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Patent number: 5888585Abstract: A charge storage device, such as an integrated circuit memory, including a dielectric comprising a barium-strontium-niobium oxide. A liquid precursor including the metals barium, strontium, and niobium is prepared and applied to a platinum electrode. The precursor is baked and annealed to form a dielectric having the formula Ba.sub.x Sr.sub.y Nb.sub.z O.sub.30, where x=1.3 to 3.5, y=1.5 to 3.7, and z =10. A top platinum electrode is then formed to provide a memory cell capacitor. Optimum results to date have been obtained with Ba.sub.2 Sr.sub.3 Nb.sub.10 O.sub.30, which yields a memory cell dielectric with dielectric constant over 1000 and a leakage current of less than 10.sup.-5 amperes per square centimeter for voltages up to 5 volts.Type: GrantFiled: December 16, 1996Date of Patent: March 30, 1999Assignee: Symetrix CorporationInventors: Joseph D. Cuchiaro, Vikram Joshi, Claudia P. DaCruz, John M. McNelis, Carlos A. Paz de Araujo
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Patent number: 5883828Abstract: Thin film ferroelectric materials for use in integrated memory circuits, such as FERAMS and the like, contain strontium bismuth niobium tantalate having an empirical formula SrBi.sub.2+E (Nb.sub.X Ta.sub.2-X)O.sub.9+3E/2, wherein E is a number representing an excess amount of bismuth ranging from zero to 2; and X is a number representing an excess amount of niobium ranging from 0.01 to 0.9. The thin films demonstrate an exceptional resistance to polarization imprinting when challenged with unidirectional voltage pulses.Type: GrantFiled: February 6, 1998Date of Patent: March 16, 1999Assignee: Symetrix CorporationInventors: Joseph D. Cuchiaro, Narayan Solayappan, Carlos A. Paz de Araujo, Larry D. McMillan
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Patent number: 5825057Abstract: A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.Type: GrantFiled: December 5, 1994Date of Patent: October 20, 1998Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.Inventors: Hitoshi Watanabe, Carlos A. Paz De Araujo, Hiroyuki Yoshimori, Michael C. Scott, Takashi Mihara, Joseph D. Cuchiaro, Larry D. McMillan
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Patent number: 5811847Abstract: An integrated circuit memory, MMIC, or other device including a dielectric comprising lead-tin zirconium-titanium oxide (PSZT). The proportion of tin ranges from 30% to 50% of the total amount of tin, zirconium and titanium. The dielectric is formed by applying a first liquid precursor having 10% excess lead to a substrate and heating it to form a first PSZT thin film, applying a second liquid precursor having 5% excess lead to the first thin film and heating to form a second thin film, then applying the first liquid precursor and heating to form a third thin film, and annealing the three thin films together to form a PSZT dielectric layer.Type: GrantFiled: June 28, 1996Date of Patent: September 22, 1998Assignee: Symetrix CorporationInventors: Vikram Joshi, Joseph D. Cuchiaro, Carlos A. Paz de Araujo, Larry D. McMillan