Patents by Inventor Joseph D. Cuchiaro

Joseph D. Cuchiaro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5784310
    Abstract: Thin film ferroelectric materials for use in integrated memory circuits, such as FERAMS and the like, contain strontium bismuth niobium tantalate having an empirical formula SrBi.sub.2+E (Nb.sub.X Ta.sub.2-X)O.sub.9+3E/2, wherein E is a number representing an excess amount of bismuth ranging from zero to 2; and X is a number representing an excess amount of niobium ranging from 0.01 to 0.9. The thin films demonstrate an exceptional resistance to polarization imprinting when challenged with unidirectional voltage pulses.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: July 21, 1998
    Assignee: Symetrix Corporation
    Inventors: Joseph D. Cuchiaro, Narayan Solayappan, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 5751034
    Abstract: A charge storage device, such as an integrated circuit memory, including a dielectric comprising a barium-strontium-niobium oxide. A liquid precursor including the metals barium, strontium, and niobium is prepared and applied to a platinum electrode. The precursor is baked and annealed to form a dielectric having the formula Ba.sub.x Sr.sub.y Nb.sub.z O.sub.30, where x=1.3 to 3.5, y=1.5 to 3.7, and z=10. A top platinum electrode is then formed to provide a memory cell capacitor. Optimum results to date have been obtained with Ba.sub.2 Sr.sub.3 Nb.sub.10 O.sub.30, which yields a memory cell dielectric with dielectric constant over 1000 and a leakage current of less than 10.sup.-5 amperes per square centimeter for voltages up to 5 volts.
    Type: Grant
    Filed: June 12, 1997
    Date of Patent: May 12, 1998
    Assignee: Symetrix Corporation
    Inventors: Joseph D. Cuchiaro, Vikram Joshi, Claudia P. DaCruz, John M. McNelis, Carlos A. Paz de Araujo
  • Patent number: 5723171
    Abstract: An electrode for a ferroelectric electronic device is formed on an SiO.sub.2 isolation layer by depositing an adhesion layer, such as titanium, between about 25 .ANG. and 500 .ANG. thick, then a layer of a nobel metal, such as platinum, that is at least 10 times thicker than the adhesion layer. The electrode is then annealed at a temperature higher than the minimum oxide eutectic temperature of the adhesion layer. The electrode is moved into the annealing furnace at a ramp rate such that it reaches its anneal temperature in five minutes or less. The relative thinness of the adhesion layer and the quick ramp up of the anneal causes all the titanium to be tied up in the oxide before it can diffuse through the platinum, and prevents the formation of rutile phases of the titanium and defects such as voids and hillocks in the platinum, which can destabilize the electrode.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: March 3, 1998
    Assignee: Symetrix Corporation
    Inventors: Joseph D. Cuchiaro, Larry D. McMillan, Carlos A. Paz de Araujo
  • Patent number: 5708302
    Abstract: An integrated circuit capacitor (20) includes a bottom electrode structure (24) having an adhesion metal portion (34), a noble metal portion (36), and a second noble metal layer (40). A process of manufacture includes annealing the adhesion metal portion (34) and the noble metal portion (36) prior to the deposition of second noble metal layer (40) for purposes of forming barrier region (38). The electrode (24) preferably contacts metal oxide layer (26), which is made of a perovskite or perovskite-like layered superlattice material. A temporary capping layer (59) is formed and removed in manufacture, which serves to increase polarization potential from the device by at least 40%.
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: January 13, 1998
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Masamichi Azuma, Carlos A. Paz De Araujo, Joseph D. Cuchiaro
  • Patent number: 5614018
    Abstract: A xylene exchange is performed on a stock solution of BST of greater then 99.999% purity dissolved in methoxyethanol, and a carboxylate of a dopant metal, such as magnesium 2-ethylhexanoate is added to form a precursor. The precursor is spun on a first electrode, dried at 400.degree. C. for 2 minutes, then annealed at 750.degree. C. to 800.degree. C. for about an hour to form a layer of accurately doped BST. A second electrode is deposited, patterned, and annealed at between 750.degree. C. to 800.degree. C. for about 30 minutes. Excellent leakage current results if the dopant is magnesium of about 5% molarity. For other dopants, such as Mg, Nb, Y, Bi, and Sn the preferred dopant range is 0.2% to 0.3% molarity. The magnesium-doped material is used as a buffer layer between the electrodes and BST dielectric of an undoped BST capacitor.
    Type: Grant
    Filed: July 11, 1994
    Date of Patent: March 25, 1997
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Masamichi Azuma, Carlos A. Paz De Araujo, Michael C. Scott, Joseph D. Cuchiaro
  • Patent number: 5519234
    Abstract: An integrated circuit includes a layered superlattice material having the formula A1.sub.w1.sup.+a1 A2.sub.w2.sup.+a2 . . . Aj.sub.wj.sup.+aj S1.sub.x1.sup.+s1 S2.sub.x2.sup.+s2 . . . Sk.sub.xk.sup.+ak B1.sub.y1.sup.+b1 B2.sub.y2.sup.+b2 . . . Bl.sub.yl.sup.+bl Q.sub.z.sup.-2, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . Bl represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in non-volatile memories. Others are high dielectric constant materials that do not degrade or breakdown over long periods of use and are applied in volatile memories.
    Type: Grant
    Filed: November 18, 1993
    Date of Patent: May 21, 1996
    Assignee: Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Joseph D. Cuchiaro, Michael C. Scott, Larry D. McMillan
  • Patent number: 5468679
    Abstract: A precursor comprising a medium-length ligand carboxylate, such as a metal 2-ethylhexanoate, in a xylenes solvent is applied to an integrated circuit wafer. The wafer is baked to dry the precursor, annealed to form a layered superlattice material on the wafer, then the integrated circuit is completed.
    Type: Grant
    Filed: November 18, 1993
    Date of Patent: November 21, 1995
    Assignee: Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Michael C. Scott, Joseph D. Cuchiaro, Larry D. McMillan
  • Patent number: 5463244
    Abstract: An electrically programmable antifuse element using ferroelectric materials for the insulative dielectric layer, methods for producing same, and an integrated circuit applying a plurality of ferroelectric antifuse elements in a two dimensional matrix of rows and columns for use as a programmable logic device (PLD) or as a programmable read-only memory (PROM). A ferroelectric material is formed between two conductive electrodes to create a ferroelectric antifuse element. In an alternative embodiment, a plurality of chemically distinct materials is layered to form the dielectric layer. The combined application of an AC electric field and a DC electric field breaks down the ferroelectric material to form a low-resistance conductive filament. The synergy of the two electric fields permits programming antifuse elements of the present invention by applying DC electric fields as low as 2 volts amplitude.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: October 31, 1995
    Assignee: Symetrix Corporation
    Inventors: Carlos A. P. De Araujo, Larry D. McMillan, Joseph D. Cuchiaro
  • Patent number: 5444290
    Abstract: An antifuse element has a dielectric layer comprising materials whose dielectric constant increases in the presence of a DC electric field, such as a ferroelectric. An applied AC electric field and a DC electric field breaks down the dielectric material to form a conductive filament. The AC electric field causes the physical reorientation of the electric dipole of the molecules in the ferroelectric material which creates heat within the ferroelectric material. The DC electric field enhances the heating effect of the AC electric field by enlarging the electric dipole of the ferroelectric molecules. The synergy of the two electric fields permits programming antifuse elements of the present invention by applying DC electric fields as low as 2 volts amplitude.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: August 22, 1995
    Assignee: Symetrix Corporation
    Inventors: Carlos A. Paz De Araujo, Larry D. McMillan, Joseph D. Cuchiaro
  • Patent number: 5439845
    Abstract: A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: August 8, 1995
    Assignees: Olympus Optical Co., Ltd., Symetrix Corporation
    Inventors: Hitoshi Watanabe, Carlos A. Paz De Araujo, Hiroyuki Yoshimori, Michael C. Scott, Takashi Mihara, Joseph D. Cuchiaro, Larry D. McMillan
  • Patent number: 5434102
    Abstract: A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: July 18, 1995
    Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.
    Inventors: Hitoshi Watanabe, Carlos A. Paz De Araujo, Hiroyuki Yoshimori, Michael C. Scott, Takashi Mihara, Joseph D. Cuchiaro, Larry D. McMillan
  • Patent number: 5423285
    Abstract: A precursor comprising a metal 2-ethylhexanoate in a xylenes solvent is applied to an integrated circuit wafer. The wafer is baked to dry the precursor, annealed to form a layered superlattice material on the wafer, then the integrated circuit is completed. If the metal is titanium, the precursor comprises titanium 2-methoxyethoxide having at least a portion of its 2-methoxyethoxide ligands replaced by 2-ethylhexanoate. If the metal is a highly electropositive element, the solvent comprises 2-methoxyethanol. If the metal is lead, bismuth, thallium, or antimony, 1% to 75% excess metal is included in the precursor to account for evaporation of the oxide during baking and annealing.
    Type: Grant
    Filed: November 24, 1992
    Date of Patent: June 13, 1995
    Assignees: Olympus Optical Co., Ltd., Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Joseph D. Cuchiaro, Michael C. Scott, Larry D. McMillan