Patents by Inventor Joseph DALTON
Joseph DALTON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110241082Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: June 20, 2011Publication date: October 6, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 8013342Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: November 14, 2007Date of Patent: September 6, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 8004289Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.Type: GrantFiled: August 26, 2008Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Thomas Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Stephen Ellinwood Luce, Edmund Juris Sprogis
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Patent number: 7960245Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: GrantFiled: February 12, 2008Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
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Patent number: 7943412Abstract: A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material.Type: GrantFiled: December 10, 2002Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Leena Paivikki Buchwalter, Kevin Kok Chan, Timothy Joseph Dalton, Christopher Vincent Jahnes, Jennifer Louise Lund, Kevin Shawn Petrarca, James Louis Speidell, James Francis Ziegler
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Publication number: 20110109405Abstract: A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.Type: ApplicationFiled: January 14, 2011Publication date: May 12, 2011Applicant: International Business Machines CorporationInventors: Leena Paivikki Buchwalter, Kevin Kok Chan, Timothy Joseph Dalton, Christopher Vincent Jahnes, Jennifer Louise Lund, Kevin Shawn Petrarca, James Louis Speidell, James Francis Ziegler
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Patent number: 7939914Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: GrantFiled: February 12, 2008Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
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Patent number: 7923712Abstract: A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element thereby reducing the contact area between the phase change element and the first electrode and thereby increasing the current density through the phase change element and effectively inducing the phase change at lower levels of current and reduced programming power.Type: GrantFiled: June 26, 2009Date of Patent: April 12, 2011Assignee: International Business Machines CorporationInventors: John Christopher Arnold, Lawrence Alfred Clevenger, Timothy Joseph Dalton, Michael Christopher Gaidis, Louis L. Hsu, Carl John Radens, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 7906428Abstract: The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.Type: GrantFiled: May 15, 2008Date of Patent: March 15, 2011Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Timothy Joseph Dalton, Louis C. Hsu, Conal Eugene Murray, Carl Radens, Kwong-Hon Wong, Chih-Chao Yang
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Patent number: 7851321Abstract: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.Type: GrantFiled: January 5, 2009Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Lawrence Clevenger, Timothy Joseph Dalton, Louis Hsu, Carl Radens, Vidhya Ramachandran, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 7670927Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: May 16, 2006Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20100001253Abstract: A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element thereby reducing the contact area between the phase change element and the first electrode and thereby increasing the current density through the phase change element and effectively inducing the phase change at lower levels of current and reduced programming power.Type: ApplicationFiled: June 26, 2009Publication date: January 7, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Christopher Arnold, Lawrence Alfred Clevenger, Timothy Joseph Dalton, Michael Christopher Gaidis, Louis L. Hsu, Carl John Radens, Keith Kwong Hon Wong, Chih-Chao Yang
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Publication number: 20090121260Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: November 14, 2007Publication date: May 14, 2009Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20090121287Abstract: A semiconductor device having wiring levels on opposite sides, a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides, and a design structure of a semiconductor device having wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: ApplicationFiled: November 14, 2007Publication date: May 14, 2009Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
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Patent number: 7531407Abstract: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.Type: GrantFiled: July 18, 2006Date of Patent: May 12, 2009Assignee: International Business Machines CorporationInventors: Lawrence Clevenger, Timothy Joseph Dalton, Louis Hsu, Carl Radens, Vidhya Ramachandran, Keith Kwong Hon Wong, Chih-Chao Yang
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Publication number: 20090108381Abstract: A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material.Type: ApplicationFiled: December 10, 2002Publication date: April 30, 2009Applicant: International Business Machines CorporationInventors: Leena Paivikki Buchwalter, Kevin Kok Chan, Timothy Joseph Dalton, Christopher Vincent Jahnes, Jennifer Louise Lund, Kevin Shawn Petrarca, James Louis Speidell, James Francis Ziegler
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Publication number: 20090111235Abstract: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.Type: ApplicationFiled: January 5, 2009Publication date: April 30, 2009Inventors: Lawrence Clevenger, Timothy Joseph Dalton, Louis Hsu, Carl Radens, Vidhya Ramachandran, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 7526698Abstract: A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.Type: GrantFiled: March 23, 2006Date of Patent: April 28, 2009Assignee: International Business Machines CorporationInventors: Timothy Joseph Dalton, Marc Raymond Faucher, Paul David Kartschoke, Peter Anthony Sandon
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Patent number: 7474104Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.Type: GrantFiled: November 8, 2006Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Thomas Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffee, Stephen Ellinwood Luce, Edmund Juris Sprogis
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Patent number: 7473979Abstract: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.Type: GrantFiled: May 30, 2006Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Lawrence Clevenger, Timothy Joseph Dalton, Louis Hsu, Carl Radens, Vidhya Ramachandran, Keith Kwong Hon Wong, Chih-Chao Yang