Patents by Inventor Joseph DALTON
Joseph DALTON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7060624Abstract: Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.Type: GrantFiled: August 13, 2003Date of Patent: June 13, 2006Assignee: International Business Machines CorporationInventors: Panayotis Andricacos, Emanuel Israel Cooper, Timothy Joseph Dalton, Hariklia Deligianni, Daniel Guidotti, Keith Thomas Kwietniak, Michelle Leigh Steen, Cornelia Kang-I Tsang
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Patent number: 7014958Abstract: A photomask is formed by depositing an opaque layer on a transparent substrate. A resist is formed on the opaque layer and selectively patterned to expose the portions of the opaque layer that are to be etched out. During the dry etching step, the photomask is exposed to an etchant gas mixture which exhibit a selectivity equal to or higher than 1.2:1 between the opaque layer and the resist layer. Due to the higher selectivity of the gas mixture, a thinner resist film can be used, thereby increasing resolution and accuracy of the opaque layer pattern. Also, due to reduced susceptibility to both a macro-loading effect and a pattern density effect, overetching of the resist and underetching of the opaque layer are significantly reduced, thereby achieving improved etching uniformity and consequently improved CD uniformity.Type: GrantFiled: June 30, 2003Date of Patent: March 21, 2006Assignee: International Business Machines CorporationInventors: Timothy Joseph Dalton, Thomas Benjamin Faure, Michelle Leigh Steen
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Publication number: 20040265703Abstract: A photomask is formed by depositing an opaque layer on a transparent substrate. A resist is formed on the opaque layer and selectively patterned to expose the portions of the opaque layer that are to be etched out. During the dry etching step, the photomask is exposed to an etchant gas mixture which exhibit a selectivity equal to or higher than 1.2:1 between the opaque layer and the resist layer. Due to the higher selectivity of the gas mixture, a thinner resist film can be used, thereby increasing resolution and accuracy of the opaque layer pattern. Also, due to reduced susceptibility to both a macro-loading effect and a pattern density effect, overetching of the resist and underetching of the opaque layer are significantly reduced, thereby achieving improved etching uniformity and consequently improved CD uniformity.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Joseph Dalton, Thomas Benjamin Faure, Michelle Leigh Steen
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Patent number: 6831364Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus forming a dielectric material that has a low dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.Type: GrantFiled: August 1, 2002Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Timothy Joseph Dalton, Stephen Edward Greco, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Kenneth Parker Rodbell, Robert Rosenberg
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Patent number: 6815329Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.Type: GrantFiled: April 2, 2002Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Katherina E. Babich, Roy Arthur Carruthers, Timothy Joseph Dalton, Alfred Grill, Jeffrey Curtis Hedrick, Christopher Vincent Jahnes, Ebony Lynn Mays, Laurent Perraud, Sampath Purushothaman, Katherine Lynn Saenger
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Patent number: 6784485Abstract: A semiconductor device containing a diffusion barrier layer is provided. The semiconductor device includes at least a semiconductor substrate containing conductive metal elements; and, a diffusion barrier layer applied to at least a portion of the substrate in contact with the conductive metal elements, the diffusion barrier layer having an upper surface and a lower surface and a central portion, and being formed from silicon, carbon, nitrogen and hydrogen with the nitrogen being non-uniformly distributed throughout the diffusion barrier layer. Thus, the nitrogen is more concentrated near the lower and upper surfaces of the diffusion barrier layer as compared to the central portion of the diffusion barrier layer. Methods for making the semiconductor devices are also provided.Type: GrantFiled: February 11, 2000Date of Patent: August 31, 2004Assignee: International Business Machines CorporationInventors: Stephan Alan Cohen, Timothy Joseph Dalton, John Anthony Fitzsimmons, Stephen McConnell Gates, Lynne M. Gignac, Paul Charles Jamison, Kang-Wook Lee, Sampath Purushothaman, Darryl D. Restaino, Eva Simonyi, Horatio Seymour Wildman
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Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
Publication number: 20040115921Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.Type: ApplicationFiled: December 11, 2002Publication date: June 17, 2004Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, Infineon Technologies North America Corp.Inventors: Larry Clevenger, Timothy Joseph Dalton, Mark Hoinkis, Staffen K. Kaldor, Kaushik Kumar, Douglas C. La Tulipe, Soon-Cheon Seo, Andrew Herbert Simon, Yun-Yu Wang, Chih-Chao Yang, Haining Yang -
Patent number: 6724069Abstract: A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.Type: GrantFiled: April 5, 2001Date of Patent: April 20, 2004Assignee: International Business Machines CorporationInventors: Timothy Joseph Dalton, Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Christy Sensenich Tyberg
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Publication number: 20040051178Abstract: A metal plus low dielectric constant (low-k) interconnect structure is provided for a semiconductor device wherein adjacent regions in a surface separated by a dielectric have dimensions in width and spacing in the sub 250 nanometer range, and in which reduced lateral leakage current between adjacent metal lines, and a lower effective dielectric constant than a conventional structure, is achieved by the positioning of a differentiating or mask member that is applied for the protection of the dielectric in subsequent processing operations, at a position about 2-5 nanometers below a, to be planarized, surface where there will be a lower electric field.Type: ApplicationFiled: September 12, 2003Publication date: March 18, 2004Applicant: International Business Machines CorporationInventors: Stephen Alan Cohen, Timothy Joseph Dalton, John Anthony Fitzsimmons, Stephen McConnell Gates, Brian Wayne Herbst, Sampath Purushothaman, Stanley Joseph Whitehair
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Patent number: 6657305Abstract: A metal plus low dielectric constant (low-k) interconnect structure is provided for a semiconductor device wherein adjacent regions in a surface separated by a dielectric have dimensions in width and spacing in the sub 250 nanometer range, and in which reduced lateral leakage current between adjacent metal lines, and a lower effective dielectric constant than a conventional structure, is achieved by the positioning of a differentiating or mask member that is applied for the protection of the dielectric in subsequent processing operations, at a position about 2-5 nanometers below a, to be planarized, surface where there will be a lower electric field.Type: GrantFiled: November 1, 2000Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Stephen Alan Cohen, Timothy Joseph Dalton, John Anthony Fitzsimmons, Stephen McConnell Gates, Brian Wayne Herbst, Sampath Purushothaman, Stanley Joseph Whitehair
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Patent number: 6548901Abstract: An interconnect structure having reduced fringing fields of bottom corners of said interconnect structure and a method of fabricating the same is provided. The interconnect structure includes one or more interconnect levels one on top of each other, wherein each interconnect level is separated by a diffusion barrier and includes a dielectric stack of at least one low-k interlayer dielectric on at least one hybrid dielectric, said dielectrics having planar interfaces therebetween, each interconnect level further comprising metallic lines formed in said low-k interlayer dielectric, with the proviso that bottom horizontal portions of said metallic lines are not coincident with said interface, and said metallic lines are contained within said low-k interlayer dielectric. The interconnect structures may be fabricated such that top horizontal portions of the metallic lines are coplanar with a top surface of the low-k interlayer dielectric.Type: GrantFiled: June 15, 2000Date of Patent: April 15, 2003Assignee: International Business Machines CorporationInventors: William Cote, Timothy Joseph Dalton, Daniel Charles Edelstein, Stephen McConnell Gates
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Publication number: 20030057414Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving as dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6.Type: ApplicationFiled: August 1, 2002Publication date: March 27, 2003Applicant: International Business Machines CorporationInventors: Timothy Joseph Dalton, Stephen Edward Greco, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Kenneth Parker Rodbell, Robert Rosenberg
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Publication number: 20020158337Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.Type: ApplicationFiled: April 2, 2002Publication date: October 31, 2002Inventors: Katherina E. Babich, Roy Arthur Carruthers, Timothy Joseph Dalton, Alfred Grill, Jeffrey Curtis Hedrick, Christopher Vincent Jahnes, Ebony Lynn Mays, Laurent Perraud, Sampath Purushothaman, Katherine Lynn Saenger
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Publication number: 20020145200Abstract: A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.Type: ApplicationFiled: April 5, 2001Publication date: October 10, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Joseph Dalton, Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Christy Sensenich Tyberg
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Patent number: 6451712Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving a dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6.Type: GrantFiled: December 18, 2000Date of Patent: September 17, 2002Assignee: International Business Machines CorporationInventors: Timothy Joseph Dalton, Stephen Edward Greco, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Kenneth Parker Rodbell, Robert Rosenberg
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Publication number: 20020074659Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving a dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6.Type: ApplicationFiled: December 18, 2000Publication date: June 20, 2002Applicant: International Business Machines CorporationInventors: Timothy Joseph Dalton, Stephen Edward Greco, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Kenneth Parker Rodbell, Robert Rosenberg
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Patent number: 6114291Abstract: The present invention relates to skin cleansing bar composition in which polyalkylene glycols of very specific molecular weights are used to define compositions which are mild, foam well and provide consumer-desired sensory profiles. A significant amount of these specific PEGs must be incorporated into the bar to deliver these desired effects. To properly process such a bar composition, the cast-melt method is the preferred technique.Type: GrantFiled: January 29, 1998Date of Patent: September 5, 2000Assignee: Lever Brothers Company division of Conopco, Inc.Inventors: Mengtao He, James Joseph Dalton, Kennard Daniels, Georgia Shafer, Michael Massaro
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Patent number: 6057275Abstract: A bar composition in which use of specific ratio of cationic to surfactant as been found to remarkably enhance deposition of oil/emollient benefit agent.Type: GrantFiled: January 4, 1999Date of Patent: May 2, 2000Assignee: Unilever Home & Personal Care USA, Division of Conopco, Inc.Inventors: Michael Joseph Fair, Michael Massaro, Harry Crookham, Gail Beth Rattinger, James Joseph Dalton, Terence James Farrell, Georgia Shafer
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Patent number: 5983438Abstract: A cleaning apparatus and method for removing debris from the seals of a pressurized enclosure, specifically a sputter load lock chamber. The cleaning apparatus includes a load lock replacement door, a cleaning tool, and a seal. The load lock replacement door includes a surface that seals the opening of the load lock chamber so as to maintain a desired vacuum pressure in the load lock chamber. The sealing surface supports a cleaning tool. The cleaning tool and the sealing surface are supported by a vacuum seal which limits leakage of gas at ambient conditions into the load lock chamber. Once the tool is installed, the load lock chamber is pumped-down to a desired vacuum pressure. The tool is manipulated as necessary to remove debris from the seals of the load lock chamber. Once the cleaning process has been completed, the load lock chamber is vented, the tool removed, and the load lock door closed and sealed.Type: GrantFiled: March 13, 1998Date of Patent: November 16, 1999Assignees: Sony Corporation, Sony Electronics, Inc.Inventors: Kenneth Mark Bostick, William Joseph Dalton