Abstract: A method for making contact to a small area field effect transistor device is described. A monocrystalline semiconductor body having at least a surface region of a first conductivity is provided with a insulating layer over the surface region. A substantially horizontal first conductive layer is formed over the insulating layer. The insulating and first conductive layers are masked and etched to form openings in the layers to the semiconductor body where the source, drain and gate region of the device is desired to be formed. The openings have substantially vertical surfaces on the layered structure. A conformal, highly doped of a second conductivity conductive layer is formed over the openings having these substantially vertical surfaces and over the insulating and conductive layers.

Abstract: The method of planarizing polysilicon-filled trenches involves first filling the trenches with an undoped polysilicon until the upper surface is substantially planar. The polycrystalline silicon is then heavily doped by means of diffusion of a dopant from the upper surface. The time and temperature of the diffusion are carefully controlled providing for the dopant to penetrate the polysilicon to a depth level with the tops of the trenches. A selective etchant is then utilized which removes the heavily doped polysilicon and leaves the undoped polysilicon untouched in the trenches.

Abstract: A semiconductor body having surface regions thereof isolated from other such regions by a pattern of dielectric isolation is provided. At least two narrow widths PN junction regions are located within at least one of the surface regions. Each PN junction has a width dimension substantially that of its electrical contact. Substantially vertical conformal conductive layers electrically ohmic contact each of the PN junction regions. The PN junction regions are the emitter and collector regions for a lateral bipolar transistor. A base PN junction region of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers are in electrical contact with an edge of each of the vertical conductive layers and separated from the surface regions by a first electrical insulating layer. A second insulating layer covers the conformal conductive layers.

Abstract: A semiconductor body having at least a surface region of a first conductivity is provided with a insulating layer over the surface region. A substantially horizontal first conductive layer is formed over the insulating layer. The insulating and first conductive layers are masked and etched to form openings in the layers to the semiconductor body where the source, drain and gate region of the device is desired to be formed. The openings have substantially vertical surfaces on the layered structure. A conformal, highly doped of a second conductivity conductive layer is formed over the openings having these vertical surfaces and over the insulating and conductive layers. The conformal layer is anisotropically etched to substantially remove the horizontal portions of the conformal layer while leaving the openings with a substantially vertical conformal conductive layer on the sides thereof.

Abstract: A method is described for forming the recessed dielectric isolation in a silicon substrate involves first forming trenches which may be less than about 1 micron in depth in areas of one principal surface of the silicon substrate where isolation is desired. Where, for example, an NPN bipolar transistor structure is planned to be formed it is usually necessary to have a P+ region underneath the recessed dielectric isolation to allow full isolation between the various bipolar transistor devices. A PNP transistor uses an N+ region underneath the isolation. Where a field effect transistor is planned a channel stop can be substituted for the P+ region. Under the circumstance of bipolar devices, the P+ region is formed in the substrate prior to the deposition of an epitaxial layer thereover. The trench formation is caused to be formed through the epitaxial layer and into the P+ regions therein. The surface of the trenches are then oxidized in an oxidizing ambient to form a silicon dioxide layer thereon.

Abstract: In a field effect device such as a charge coupled device or field effect transistor in which at least two levels of polycrystalline silicon conductors are used; these two levels of polycrystalline silicon are isolated from one another with a dielectric layer. Disclosed is a composite dielectric layer formed either by in situ oxidation of the first polycrystalline silicon layer plus chemical vapor deposited silicon dioxide or, in the alternative, the composite dielectric layer is formed by a phosphosilicate glass layer with thermal reoxidation of the first polycrystalline silicon layer.

Abstract: A contact structure in a double polysilicon device is described in which direct shorts between overlying polysilicon conductors due to a "polysilicon void phenomenon" is overcome by patterning an appropriate etch stop between the conductors.

Abstract: A dielectrically isolated region of a monocrystalline substrate, which has a <100> orientation, has a drain region of a field effect transistor (FET) in a surface having a (100) crystal orientation with the drain region being of opposite conductivity to the conductivity of the substrate. A gate channel extends into the substrate from the drain region and is surrounded at its upper end by the drain region. An enlarged recess extends into the substrate beneath the gate channel and has its walls of opposite conductivity to the conductivity of the substrate to form a source region and a plate of a capacitor when the FET is part of a storage cell. The source region has its upper end surrounded by the gate channel.

Abstract: A conductor bit line for a dynamic random access memory (RAM) structure is formed of a material selected from the group consisting of polycrystalline silicon and a metal silicide, polycrystalline silicon and a conductive metal, and polycrystalline silicon, a metal silicide, and a conductive metal with the polycrystalline silicon contacting at least a portion of the drain region of the field effect transistor of each of a plurality of cells of the RAM structure via a self-aligned contact. When the selected material is polycrystalline silicon and a metal silicide, the conductor bit line is continuous.

Abstract: A contact structure in a double polysilicon device is described in which direct shorts between overlying polysilicon conductors due to a "polysilicon void phenomenon" is overcome by patterning an appropriate etch stop between the conductors.

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The intrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing.

Abstract: A buried electrical contact is made to a substrate of monocrystalline silicon through a relatively thin layer of silicon dioxide without causing damage to the relatively thin layer of silicon dioxide. This is accomplished through depositing a thin layer of polycrystalline silicon over the relatively thin layer of silicon dioxide prior to forming the opening in the relatively thin layer of silicon dioxide for the electrical contact to the substrate. After the thin layer of polycrystalline silicon is deposited, an opening is formed therein so that the thin layer of polycrystalline silicon functions as a mask to etch a corresponding opening in the relatively thin layer of silicon dioxide. Then, a layer of polycrystalline silicon is deposited over the exposed surface of the substrate and the thin layer of polycrystalline silicon to form the electrical contact through the opening in the relatively thin layer of silicon dioxide to the substrate.

Abstract: In a field effect device such as a charge coupled device or field effect transistor in which at least two levels of polycrystalline silicon conductors are used; these two levels of polycrystalline silicon are isolated from one another with a dielectric layer. Disclosed is a composite dielectric layer formed either by in situ oxidation of the first polycrystalline silicon layer plus chemical vapor deposited silicon dioxide or, in the alternative, the composite dielectric layer is formed by a phosphosilicate glass layer with thermal reoxidation of the first polycrystalline silicon layer.

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing.

Abstract: In a field effect device such as a charge coupled device or field effect transistor in which at least two levels of polycrystalline silicon conductors are used; these two levels of polycrystalline silicon are isolated from one another with a dielectric layer. Disclosed is a dielectric layer of reflowed phosphosilicate glass (PSG) on top surfaces of a polycrystalline silicon layer which may be doped by phosphorous impurities diffusing from the PSG.