Abstract: A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. The structure can be readily and easily planarized, particularly if a polish-stop layer is applied over the body of semiconductor material and voids and contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on a resist used to form the trench.

Abstract: A DRAM cell of the trench capacitor type is formed by a simplified process that reduces cost and increases process latitude by forming the trench collar in a single step of expanding a shallow trench horizontally and conformally coating the collar; etching the trench to its final depth and implanting the bottom heavily and doping the walls lightly; recessing the poly liner in a non-critical step that exposes a contact area between the top of the poly and the adjacent transistor electrode.

Abstract: A trench capacitor DRAM cell with Shallow Trench Isolation (STI), a self-aligned buried strap and the method of making the cell. A trench capacitor is defined in a substrate. The trench capacitor's polysilicon (poly) plate is recessed below the surface of the substrate and the trench sidewalls are exposed above the poly. A doped poly layer is deposited over the surface contacting both the sidewall and the trench capacitor's poly plate. Horizontal portions of the poly layer are removed either through chemmech polishing or Reactive Ion Etching (RIE). A shallow trench is formed, removing one formerly exposed trench sidewall and a portion of the trench capacitor's poly plate in order to isolate the DRAM cell from adjacent cells. The remaining poly strap, along the trench sidewall contacting the poly plate, is self aligned to contact the source of the DRAM Pass gate Field Effect Transistor (FET). After the shallow trench is filled with oxide, FET's are formed on the substrate, completing the cell.

Abstract: A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain combine with nitride sidewalls on a gate contact aperture to separate a gate contact from source and drain contacts.

Abstract: A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.

Abstract: A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices.

Abstract: A method of forming a MOS FET in which the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The sidewalls that are used to form an LDD source and drain separate a gate contact from source and drain contacts.

Abstract: A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain form a self-aligned aperture for a surface strap that insulates the strap from misaligned portions of the gate stack.

Abstract: A method of thinning SOI films for providing ultra-thin active device regions having excellent thickness uniformity and further having self-aligned isolation regions between the active device regions is disclosed. A substrate having an isolation layer formed thereon and further having a single crystal silicon layer formed upon the isolation layer is first provided. A thermal oxide layer is grown upon the silicon layer, patterned in desired regions corresponding to polish stop regions positioned between predetermined active device regions, and etched. The silicon layer is thereafter etched according to the patterned thermal oxide layer with a high selectivity etch, thereby creating grooves in the silicon layer.

Abstract: A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices.

Abstract: A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.

Abstract: A lightly doped drain, field effect transistor with an inverted "T"-gate structure has a gate electrode disposed on a polysilicon pad in a stack opening. The inner edge of a lightly-doped source and drain region is aligned with the gate electrode and its outer edge is aligned with an edge of the polysilicon pad. The inner edge of a heavily-doped source and drain region is aligned with the edge of the edge of the polysilicon pad and its outer edge is aligned with the wall surface that forms the opening. The inner edge of a source and drain contact region is aligned with the wall and extends under the stack.

Abstract: A process for making local interconnection of devices on a semiconductor substrate is disclosed. Contact openings are defined to a plurality of devices on the substrate. A blanket layer of germanium is deposited over the substrate, followed by deposition of a blanket layer of electrically conducting material on top of the germanium layer. The conducting layer is etched first stopping at the germanium layer. Subsequently the germanium layer is etched by a different process, selective to the conductive layer and the device contact. The conducting layer is preferably one of the following materials: polysilicon, silicide, a composite of polysilicon with metal or silicide films.

Abstract: A method of forming an LDD field effect transistor with an inverted "T"-gate structure in which consecutive, conformal layers of polysilicon, metal and nitride or oxide are deposited to fill the recess in a composite interconnect layer on top of a trench isolated region of a semiconductor substrate. These conformal layers successively decrease in thickness and are selectively etched in two steps to form a self-aligned inverted T structure. A first reactive ion etch (RIE) step preferentially etches the exposed outer polysilicon to a certain depth. During a second step RIE the polysilicon layer is completely etched down to the a gate oxide surface and the metal layer is preferentially etched so that subtends only the remaining nitride or oxide cap.

Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled submicron-wide emitter. In one embodiment, the emitter is contacted by a self-aligned conductive sidewall linked up to a horizontal conductive link. The extrinsic base, embedded within the collector, is recessed below and laterally spaced from the emitter by an insulator layer formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In a third embodiment, the emitter is ring shaped. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area.A novel process of forming vertical (e.g.

Abstract: Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image size is achieved by establishing sidewalls to the interior vertical surfaces of the opening by depositing a conformal layer, followed by anisotropic etching. The dimension of the opening is reduced by the combined thickness of the two opposite insulator sidewalls.In a specific direct application of the disclosed process, a photomask/stencil having a pattern of openings of a minimum size smaller than possible by lighography, per se, is formed.

Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled sub-micron-wide emitter. In one embodiment, the emitter is contacted by a self-aligned conductive sidewall linked up to a horizontal conductive link. The extrinsic base, embedded within the collector, is recessed below and laterally spaced from the emitter by an insulator layer formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In a third embodiment, the emitter is ring shaped. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area.

Abstract: Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image size is achieved by establishing sidewalls to the interior vertical surfaces of the opening by depositing a conformal layer, followed by anisotropic etching. The dimension of the opening is reduced by the combined thickness of the two opposite insulator sidewalls.In a specific direct application of the disclosed process, a photomask/stencil having a pattern of openings of a minimum size smaller than possible by lithography, per se, is formed.

Abstract: A method is disclosed for making submicron openings in a substrate. A mesa is formed on the substrate by reactive ion etching techniques. A film is deposited over the entire structure and the mesa is selectively etched away to yield a submicron-sized opening in the film. Using the film as a mask, the substrate exposed thereby is reactively ion etched. An example is given for producing an emitter mask for a polycrystalline silicon base bipolar transistor.

Abstract: An integrated circuit structure which includes small area lateral bipolar and method for making the same is described. A semiconductor body, such as a monocrystalline silicon wafer, having surface regions thereof isolated from other such regions by a pattern of dielectric isolation is provided. At least two narrow widths PN junction regions are located within at least one of the surface regions. Each PN junction has a width dimension substantially that of its electrical contact. Substantially vertical conformal conductive layers electrically ohmic contact each of the PN junction regions. The PN junction regions are the emitter and collector regions for a lateral bipolar transistor. A base PN junction base region of an opposite conductivity is located between and contiguous to the emitter and the collector junctions.