Patents by Inventor Joseph Fauty

Joseph Fauty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080006920
    Abstract: In one exemplary embodiment, a multi-chip semiconductor connector is utilized for forming a semiconductor package having a plurality of semiconductor die. The multi-chip semiconductor connector is utilized to mechanically attach the plurality of semiconductor die together and to provide electrical connection to the plurality of semiconductor die.
    Type: Application
    Filed: September 24, 2007
    Publication date: January 10, 2008
    Inventors: Francis Carney, Phillip Celaya, Joseph Fauty, James Letterman, Stephen St. Germain, Jay Yoder
  • Publication number: 20070126106
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.
    Type: Application
    Filed: February 7, 2007
    Publication date: June 7, 2007
    Inventors: Francis Carney, Phillip Celaya, Joseph Fauty, James Letterman, Stephen St. Germain, Jay Yoder
  • Publication number: 20070126107
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.
    Type: Application
    Filed: February 12, 2007
    Publication date: June 7, 2007
    Inventors: Francis Carney, Phillip Celaya, Joseph Fauty, James Letterman, Stephen Germain, Jay Yoder
  • Publication number: 20070117259
    Abstract: A circuit component having one or more encapsulated circuit elements that are not disposed on a rigid support substrate and a method for manufacturing the circuit component. A semiconductor wafer is disposed on a dicing film and singulated into individual semiconductor chips. The dicing film is stretched and a protective film is placed in contact with the active surfaces of the semiconductor chips. An encapsulating material is formed over the semiconductor chips. The encapsulating material covers the semiconductor chips and the portions of the protective film between the semiconductor chips to form a unitary structure. A support film is coupled to the unitary structure and the protective film is removed. The unitary structure is singulated into individual semiconductor components. Alternatively, multichip circuit components can be manufactured that may include active circuit elements, passive circuit elements, or combinations thereof.
    Type: Application
    Filed: November 18, 2005
    Publication date: May 24, 2007
    Inventors: Harold Anderson, Jay Yoder, Cang Ngo, Joseph Fauty, James Lettlerman
  • Publication number: 20070111393
    Abstract: In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 17, 2007
    Inventors: William Burghout, Francis Carney, Joseph Fauty, James Letterman, Jay Yoder
  • Publication number: 20070075409
    Abstract: In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions.
    Type: Application
    Filed: October 5, 2005
    Publication date: April 5, 2007
    Inventors: James Letterman, Kent Kime, Joseph Fauty
  • Publication number: 20070040283
    Abstract: In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.
    Type: Application
    Filed: August 18, 2005
    Publication date: February 22, 2007
    Inventors: Joseph Fauty, James Letterman, Denise Thienpont
  • Publication number: 20050285249
    Abstract: In one exemplary embodiment, a multi-chip semiconductor connector is utilized for forming a semiconductor package having a plurality of semiconductor die. The multi-chip semiconductor connector is utilized to mechanically attach the plurality of semiconductor die together and to provide electrical connection to the plurality of semiconductor die.
    Type: Application
    Filed: June 28, 2004
    Publication date: December 29, 2005
    Inventors: Francis Carney, Phillip Celaya, Joseph Fauty, James Letterman, Stephen Germain, Jay Yoder
  • Publication number: 20050287703
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.
    Type: Application
    Filed: June 28, 2004
    Publication date: December 29, 2005
    Inventors: Francis Carney, Phillip Celaya, Joseph Fauty, James Letterman, Stephen Germain, Jay Yoder
  • Publication number: 20050285235
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.
    Type: Application
    Filed: June 28, 2004
    Publication date: December 29, 2005
    Inventors: Francis Carney, Phillip Celaya, Joseph Fauty, James Letterman, Stephen St. Germain, Jay Yoder
  • Publication number: 20050127482
    Abstract: A method of forming a leadframe and a semiconductor package using the leadframe facilitates selectively forming leads for the package. The leadframe is formed with a first portion of the leads extending from a panel of the leadframe into a molding cavity section of the leadframe. After encapsultaion, a portion of the leadframe panel is used to form a second portion of the leads that is external to the package body.
    Type: Application
    Filed: December 8, 2003
    Publication date: June 16, 2005
    Inventors: Joseph Fauty, James Knapp, James Letterman