Patents by Inventor Joseph Huang

Joseph Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6825698
    Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: November 30, 2004
    Assignee: Altera Corporation
    Inventors: Bonnie I. Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Philip Pan
  • Patent number: 6825692
    Abstract: An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: November 30, 2004
    Assignee: Altera Corporation
    Inventors: Jonathan Chung, In Whan Kim, Philip Pan, Chiakang Sung, Bonnie Wang, Xiaobao Wang, Yan Chong, Gopinath Rangan, Khai Nguyen, Tzung-Chin Chang, Joseph Huang
  • Patent number: 6815981
    Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: November 9, 2004
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, Srinivas T. Reddy, David Edward Jefferson, Rina Raman, L. Todd Cope, Christopher F. Lane, Joseph Huang, Francis B. Heile, Bruce B. Pedersen, David Wolk Mendel, Craig Schilling Lytle, Robert Richard Noel Bielby, Kerry Veenstra
  • Patent number: 6806733
    Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: October 19, 2004
    Assignee: Altera Corporation
    Inventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
  • Patent number: 6766505
    Abstract: Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (705), and this data is also handled internally in parallel. The configuration data will be stored in a data register (722). This data register includes two or more serial register chains, each chain being made up of a serial chain of registers. The configuration data is input into the two of more chains of the data registers in parallel. Circuitry is also provided to handle redundancy.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: July 20, 2004
    Assignee: Altera Corporation
    Inventors: Gopi Rangan, Khai Nguyen, Chiakang Sung, Xiaobao Wang, In Whan Kim, Yan Chong, Philip Pan, Joseph Huang, Bonnie Wang
  • Patent number: 6747903
    Abstract: Methods and apparatus for decoding addresses in a memory to provide mixed input and output data widths. A method includes receiving an address portion comprising a first number of bits. A second number of bits of the address portion are blocked, where the second number is less than the first number. A third number of bits are not blocked, and the third number plus the second number equal the first number. The third number of bits are decoded and a fourth number of memory cells are selected. The fourth number is equal to two to the power of the second number. A fourth number of data bits are received and multiplexed to the selected memory cells. The data bits are written to the selected memory cells.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: June 8, 2004
    Assignee: Altera Corporation
    Inventors: Philip Y. Pan, Chiakang Sung, Joseph Huang, Bonnie Wang, Khai Nguyen, Xiaobao Wang, Gopinath Rangan, In Whan Kim, Yan Chong, Tzung-Chin Chang
  • Patent number: 6731142
    Abstract: A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: May 4, 2004
    Assignee: Altera Corporation
    Inventors: Bonnie Wang, Chiakang Sung, Khai Nguyen, Joseph Huang, Xiaobao Wang, In Whan Kim, Gopi Rangan, Yan Chong, Phillip Pan, Tzung-Chin Chang
  • Patent number: 6731137
    Abstract: The present invention encompasses a bus hold and weak pull-up circuit. A resistor having a first node and a second node is coupled to a bi-directional I/O pin at the first node. The weak pull-up circuit is directly coupled to the resistor at the first node. The bus hold circuit is coupled to the resistor at the second node.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: May 4, 2004
    Assignee: Altera Corporation
    Inventors: Gopinath Rangan, Chiakang Sung, Xiaobao Wang, Philip Pan, Yan Chong, In Whan Kim, Khai Nguyen, Bonnie Wang, Tzung-Chin Chang, Joseph Huang
  • Publication number: 20040066212
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Application
    Filed: January 31, 2003
    Publication date: April 8, 2004
    Applicant: Altera Corporation
    Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
  • Patent number: 6714044
    Abstract: Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (705), and this data is also handled internally in parallel. The configuration data will be stored in a data register (722). This data register is segmented into two or more segments, each segment being made up of a serial chain of registers (808). The configuration data is input into the two of more segments of the data registers in parallel. Circuitry is also provided to handle redundancy.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: March 30, 2004
    Assignee: Altera Corporation
    Inventors: Gopi Rangan, Khai Nguyen, Chiakang Sung, Xiaobao Wang, In Whan Kim, Yan Chong, Philip Pan, Joseph Huang, Bonnie Wang
  • Patent number: 6707399
    Abstract: Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: March 16, 2004
    Assignee: Altera Corporation
    Inventors: Bonnie Wang, Chiakang Sung, Khai Nguyen, Joseph Huang, Gopi Rangan, Nitin Prasad
  • Patent number: 6691267
    Abstract: A technique to implement functions requiring fewer pins of an integrated circuit to serially transfer data into the integrated circuit for multiple logic blocks. By reducing the required pins, this permits downbonding of the integrated circuit into a package with fewer pins. This technique may be used to implement test functions in a programmable logic device. Test data may be serially input using a test pin (310) for two or more columns (320) of logic blocks. The test data is stored in an A register (330), and may be later transferred into a B register (335).
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: February 10, 2004
    Assignee: Altera Corporation
    Inventors: Khai Nguyen, Chiakang Sung, Bonnie Wang, Joseph Huang, Xiaobao Wang
  • Patent number: 6686769
    Abstract: A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: February 3, 2004
    Assignee: Altera Corporation
    Inventors: Khai Nguyen, Chiakang Sung, Bonnie Wang, Joseph Huang, Phillip Pan, In Whan Kim, Gopi Rangan, Yan Chong, Xiaobao Wang, Tzung-Chin Chang
  • Patent number: 6681378
    Abstract: A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: January 20, 2004
    Assignee: Altera Corporation
    Inventors: Xiaobao Wang, Chiakang Sung, Joseph Huang, Bonnie Wang, Khai Nguyen, Richard G. Cliff
  • Patent number: 6667641
    Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: December 23, 2003
    Assignee: Altera Corporation
    Inventors: Bonnie I. Wang, Joseph Huang, Chiakang Sung, Xiaobao Wang, In Whan Kim, Wayne Yeung, Khai Nguyen
  • Patent number: 6661733
    Abstract: Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: December 9, 2003
    Assignee: Altera Corporation
    Inventors: Philip Y. Pan, Chiakang Sung, Joseph Huang, Bonnie Wang, Khai Nguyen, Xiaobao Wang, Gopinath Rangan, In Whan Kim, Yan Chong
  • Patent number: 6646467
    Abstract: A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Some of the registers on the device are closely coupled for data input and output to data signal input/output pins of the device. The clock signal input terminals of at least these registers are also closely coupled to the clock signal input pin of the device. Programmable input delay is provided between the data signal input/output pins and the data input terminals of the above-mentioned registers to help compensate for clock signal skew on the device.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: November 11, 2003
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, Francis B. Heile, Joseph Huang, David W. Mendel, Bruce B. Pendersen, Chiakang Sung, Kerry Veenstra, Bonnie I. Wang
  • Patent number: 6642758
    Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: November 4, 2003
    Assignee: Altera Corporation
    Inventors: Bonnie I. Wang, Joseph Huang, Chiakang Sung, Xiaobao Wang, In Whan Kim, Wayne Yeung, Khai Nguyen
  • Patent number: 6630844
    Abstract: A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal; levels, including low supply signal levels, while limiting leakage current effects.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: October 7, 2003
    Assignee: Altera Corporation
    Inventors: Yan Chong, Chiakang Sung, Bonnie Wang, Khai Nguyen, Joseph Huang, Xiaobao Wang, Philip Pan, In Whan Kim, Gopi Rangan, Tzung-Chin Chang, Surgey Y. Shumarayev, Thomas H. White
  • Patent number: RE38651
    Abstract: A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: November 9, 2004
    Assignee: Altera Corporation
    Inventors: Chiakang Sung, Wanli Chang, Joseph Huang, Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Bahram Ahanin