Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: An LED flashlight having a structure of switch for which the housing of the flashlight comprises a cylinder and a rotating member mutually connected by means of an outer and an inner screw thread section, the cylinder and the rotating member thus rotate relatively to each other. When the rotating member so rotates, it moves an elastic piece having a number of P typed arms; the inner wall of the cylinder has at a position contacting protruding portions of the P typed arms an annular recess. When in circuit breaking of the flashlight, the protruding portions of the arms are exactly located in the annular recess and thereby is in a state of none contact; and when the rotating member rotates relatively to the cylinder, the rotating member moves the elastic piece axially to make the protruding portions move over the annular recess to contact the inner wall, thus the LED is turned on to emit light for illumination.

Abstract: A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Some of the registers on the device are closely coupled for data input and output to data signal input/output pins of the device. The clock signal input terminals of at least these registers are also closely coupled to the clock signal input pin of the device. Programmable input delay is provided between the data signal input/output pins and the data input terminals of the above-mentioned registers to help compensate for clock signal skew on the device.

Abstract: A device for transdermal drug delivery and administration of differing dosages at specific times of the day automatically pursuant to a pre-programmed dosage profile. The device includes a control and display unit, a two-part dispensing mechanism, a drug reservoir, an administration element, and a solvent removal element. The dispensing mechanism may be a peristaltic pump having an active portion with a motor, a roller, a mounting plate and a detachable passive portion with tubing and a housing. The motor and roller are mounted in the reusable portion of the delivery device with the control unit and a power source. The speed of the micromotor is controlled by the control unit, so that the turning speed of the roller is controlled which, in turn, controls the flow rate to the administration. The passive portion and drug reservoir are detachable along with the administration element for attaching a new dosing reservoir.

Abstract: An opening of a plastic bag with an article stored therein is placed between a cover and a vacuum assembly of a pocket sealing machine. Moving a rib to a second slot will extend a suction head into the opening of the bag. Pressing the cover will enable an electric heater to start heat sealing the opening of the bag. The machine can be relatively moved across the opening of the bag until the suction head is wrapped. After disabling the electric heater, a switch activates a motor for disabling the heat sealing and enabling the suction head to make a vacuum in the bag. Releasing the switch will deactivate the motor. Moving the rib back to a first slot will retract the suction head, and the machine is moved to cover the opening of the bag. Pressing the cover toward the vacuum assembly at that time will enable the electric heater to seal the opening.

Abstract: A mixer may include one or more of (i) a readily installable and removable bowl guard member, (ii) a bowl guard sensor arrangement, (iii) a bowl guard support ring assembly including a plastic part and a metal part, (iv) a bowl guard support ring assembly and bowl guard member that interact for limiting movement of the bowl guard member.

Abstract: A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.

Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Abstract: A mixing machine includes a removable head cover that may be formed of plastic and that may include a nose portion that is disposed about a power take off the mixing machine.

Abstract: A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

Abstract: Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector and an up down counter that provides a main control signal to adjust the delay by the main variable delay circuit. When the DLL circuit is locked, an arithmetic logic unit (ALU) produces a processed control signal based on the main control signal, an ALU control signal and an offset control signal, and the processed control signal is provided to the smaller variable delay circuit. By adjusting the ALU control and offset control signals, the phase shift introduced on the DLL control signal by the smaller variable delay circuit can be adjusted. In another embodiment of the invention, a second up down counter is used in place of an ALU for providing a dynamically adjustable phase shift in accordance with the principles of the present invention.

Abstract: Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.

Abstract: Once opening of a plastic bag with an article stored therein is placed between a cover and a vacuum assembly of a pocket sealing machine, moving a rib to a second slot will extend the suction head into the opening. Pressing the cover will enable an electric heater to start heat sealing the opening, and moving the machine across the opening until the suction head is wrapped. In a suction releasing the cover will disable the electric heater, pressing a switch will activate a motor for disabling the heat sealing and enabling the suction head to make a vacuum in the bag, and releasing the switch will deactivate the motor. In a final sealing moving the rib back to a first slot will retract the suction head, moving the machine to cover the opening, and pressing the cover toward the vacuum assembly will enable the electric heater to seal the opening.

Abstract: An LED flashlight having a structure of switch for which the housing of the flashlight comprises a cylinder and a rotating member mutually connected by means of an outer and an inner screw thread section, the cylinder and the rotating member thus rotate relatively to each other. When the rotating member so rotates, it moves an elastic piece having a number of P typed arms; the inner wall of the cylinder has at a position contacting protruding portions of the P typed arms an annular recess. When in circuit breaking of the flashlight, the protruding portions of the arms are exactly located in the annular recess and thereby is in a state of none contact; and when the rotating member rotates relatively to the cylinder, the rotating member moves the elastic piece axially to make the protruding portions move over the annular recess to contact the inner wall, thus the LED is turned on to emit light for illumination.

Abstract: A memory cell of a programmable device includes a memory partitioning circuit to partition a multiple port memory device into one or more single port memory partitions. The memory partitioning circuit prevents cross addressing by setting the value of one or more address lines of each memory port to a fixed value. The memory partitioning circuit holds address lines at their required values during the programmable device's normal, clear, and reset modes of operation. The behavior of the memory partitioning circuit is set by a portion of a device configuration used to configure the programmable device. The memory partitioning circuit is connected between a memory cell's address register and row or column decoders used to access the multiple port memory device. The memory partitioning circuit can also perform bit-wise inversion operations on portions of the memory addresses.

Abstract: Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.

Abstract: A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.